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A 0.18 /spl mu/m 4Mb toggling MRAM | IEEE Conference Publication | IEEE Xplore

A 0.18 /spl mu/m 4Mb toggling MRAM


Abstract:

A low power 4Mb Magnetoresistive Random Access Memory (MRAM) with a new magnetic switching mode is presented for the first time. The memory cell is based on a 1-Transisto...Show More

Abstract:

A low power 4Mb Magnetoresistive Random Access Memory (MRAM) with a new magnetic switching mode is presented for the first time. The memory cell is based on a 1-Transistor 1-Magnetic Tunnel Junction (1TIMTJ) bit cell. The 4Mb MRAM circuit was designed in a five level metal, 0.18/spl mu/m CMOS process with a bit cell size of 1.55/spl mu/m/sup 2/. A new cell architecture, bit structure, and switching mode improve the operational performance of the MRAM as compared to conventional MRAM. The 4Mb circuit is the largest MRAM memory demonstration to date.
Date of Conference: 08-10 December 2003
Date Added to IEEE Xplore: 03 March 2004
Print ISBN:0-7803-7872-5
Conference Location: Washington, DC, USA

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