Abstract:
In this work, based on the concept of test pattern broadcasting, we propose a new core-based testing method which gives core users the maximum level of test freedom. Inst...Show MoreMetadata
Abstract:
In this work, based on the concept of test pattern broadcasting, we propose a new core-based testing method which gives core users the maximum level of test freedom. Instead of only using the test patterns delivered by core providers, core users are allowed to broadcast their own test patterns to the cores of a SoC (system on chip) design for parallel scan testing. The fault coverage of each core test, using test patterns developed by any core user, can be evaluated by an enhanced version of a traditional fault simulator. The netlist of each core is scrambled before it is delivered to core users, thus the netlist will not be revealed. The enhanced fault simulator of a core has the capabilities of decoding the scrambled netlist, and performing fault simulation for the test patterns provided by each of the core users. For each core, both random test patterns (applied by a core user), and golden test patterns (delivered by the core provider) jointly achieve high and flexible fault coverage requirements. The enhanced logic simulator of each core can also decrypt the scrambled netlist, and perform logic simulation with the objective of generating fault-free test responses for signature analysis (for example). The proposed method has the advantages of minimizing the number of scan pins, reducing the test application time, and achieving the maximum level of test quality control by core users. Simulation results demonstrate the feasibility of this method.
Published in: IEEE Transactions on Reliability ( Volume: 52, Issue: 4, December 2003)
ALi Corporation, Taipei, Taiwan
J.H.Jiang was born in Taipei, Taiwan, R.O.C. She received the M.S. degree in Computer Science and Information Engineering from National Chung-Cheng University in 2000. She is currently a design engineer of IC chips in ALi Corporation, Taipei, Taiwan, R.O.C. Her research interests include design for testability and core-based testing for SoC.
J.H.Jiang was born in Taipei, Taiwan, R.O.C. She received the M.S. degree in Computer Science and Information Engineering from National Chung-Cheng University in 2000. She is currently a design engineer of IC chips in ALi Corporation, Taipei, Taiwan, R.O.C. Her research interests include design for testability and core-based testing for SoC.View more
ECECS Department, University of Cincinnati, OH, USA
Wen-Ben Jone was born in Taipei, Taiwan, Republic of China. He received the B.S. degree in Computer Science in 1979, the M.S. degree in Computer Engineering in 1981, both from National Chiao-Tung University, Hsin-Chu, Taiwan; and the Ph.D. degree in Computer Engineering and Science from Case Western Reserve University, Cleveland, OH, in 1987.
In 1987, he joined the Department of Computer Science at New Mexico Institute of ...Show More
Wen-Ben Jone was born in Taipei, Taiwan, Republic of China. He received the B.S. degree in Computer Science in 1979, the M.S. degree in Computer Engineering in 1981, both from National Chiao-Tung University, Hsin-Chu, Taiwan; and the Ph.D. degree in Computer Engineering and Science from Case Western Reserve University, Cleveland, OH, in 1987.
In 1987, he joined the Department of Computer Science at New Mexico Institute of ...View more
CS Department, National Tsing Hua University, Hsinchu, Taiwan
Shih-Chieh Chang received the B.S. degree in Electrical Engineering from National Taiwan University in 1987 and the Ph.D. degree in Electrical Engineering from the University of California, Santa Barbara, in 1994. He worked at Synopsys, Inc., Mountain View, CA, from 1995 to 1996. He then joined the faculty at the Institute of Computer Science and Information Engineering, National Chung Cheng University, Taiwan from 1996 t...Show More
Shih-Chieh Chang received the B.S. degree in Electrical Engineering from National Taiwan University in 1987 and the Ph.D. degree in Electrical Engineering from the University of California, Santa Barbara, in 1994. He worked at Synopsys, Inc., Mountain View, CA, from 1995 to 1996. He then joined the faculty at the Institute of Computer Science and Information Engineering, National Chung Cheng University, Taiwan from 1996 t...View more
ECECS Department, University of Cincinnati, OH, USA
Swaroop Ghosh received the B.E. degree in Electrical Engineering from the University of Roorkee (Now Indian Institute of Technology, Roorkee), India, in 2000. He worked at Mindtree Technologies Pvt. Ltd., Bangalore, India as a VLSI Design Engineer before joining the ECECS Department at University of Cincinnati in September 2002. His research interests are in the fields of digital testing and very large scale integrated ci...Show More
Swaroop Ghosh received the B.E. degree in Electrical Engineering from the University of Roorkee (Now Indian Institute of Technology, Roorkee), India, in 2000. He worked at Mindtree Technologies Pvt. Ltd., Bangalore, India as a VLSI Design Engineer before joining the ECECS Department at University of Cincinnati in September 2002. His research interests are in the fields of digital testing and very large scale integrated ci...View more
Contents ALi Corporation, Taipei, Taiwan
J.H.Jiang was born in Taipei, Taiwan, R.O.C. She received the M.S. degree in Computer Science and Information Engineering from National Chung-Cheng University in 2000. She is currently a design engineer of IC chips in ALi Corporation, Taipei, Taiwan, R.O.C. Her research interests include design for testability and core-based testing for SoC.
J.H.Jiang was born in Taipei, Taiwan, R.O.C. She received the M.S. degree in Computer Science and Information Engineering from National Chung-Cheng University in 2000. She is currently a design engineer of IC chips in ALi Corporation, Taipei, Taiwan, R.O.C. Her research interests include design for testability and core-based testing for SoC.View more
ECECS Department, University of Cincinnati, OH, USA
Wen-Ben Jone was born in Taipei, Taiwan, Republic of China. He received the B.S. degree in Computer Science in 1979, the M.S. degree in Computer Engineering in 1981, both from National Chiao-Tung University, Hsin-Chu, Taiwan; and the Ph.D. degree in Computer Engineering and Science from Case Western Reserve University, Cleveland, OH, in 1987.
In 1987, he joined the Department of Computer Science at New Mexico Institute of Mining and Technology, Socorro, New Mexico, where he was promoted as an Associate Professor in 1992. From 1993 to 2000, he was with the Department of Computer Engineering and Information Science, National Chung-Cheng University, Chiayi, Taiwan, R.O.C. He was a visiting research fellow with the Department of Computer Science and Engineering, the Chinese University of Hong-Kong, in 1997 summer. In 2001, he joined the Department of Electrical & Computer Engineering and Computer Science, University of Cincinnati, Ohio, USA. He was a visiting scholar with the Institute of Information Science, Academia Sinica, Taiwan, Republic of China, in 2002 summer. His research interests include VLSI design for testability, built-in self-testing, memory testing, high-performance circuit testing, MEMS testing and repairing, and low-power circuit design. He has published more than 100 papers and holds one patent (USA).
Dr. Jone served as a reviewer in these research areas in various technical journals and conferences. He is also listed in the Marquis Who's Who in the World (15th Edition, 1998, 2001). He also served on the program committee of VLSI Design/CAD Symposium (1993–1997, in Taiwan), was the General Chair of 1998 VLSI Design/CAD Symposium, served on the program committee of 1995, 1996, 2000 Asian Test Conference, 1995–1998 Asia and South Pacific Design Automation Conference, 1998 International Conference on Chip Technology, 2000 International Symposium on Defect and Fault Tolerance in VLSI Systems, and 2002, 2003 Great Lake Symposium on VLSI. He received the Best Thesis Award from The Chinese Institute of Electrical Engineering, (Republic of China), in 1981. He is a co-recipient of the 2003 IEEE Donald G. Fink Prize Paper Award. He is a senior member of IEEE and the IEEE Computer Society Test Technology Technical Committee.
Wen-Ben Jone was born in Taipei, Taiwan, Republic of China. He received the B.S. degree in Computer Science in 1979, the M.S. degree in Computer Engineering in 1981, both from National Chiao-Tung University, Hsin-Chu, Taiwan; and the Ph.D. degree in Computer Engineering and Science from Case Western Reserve University, Cleveland, OH, in 1987.
In 1987, he joined the Department of Computer Science at New Mexico Institute of Mining and Technology, Socorro, New Mexico, where he was promoted as an Associate Professor in 1992. From 1993 to 2000, he was with the Department of Computer Engineering and Information Science, National Chung-Cheng University, Chiayi, Taiwan, R.O.C. He was a visiting research fellow with the Department of Computer Science and Engineering, the Chinese University of Hong-Kong, in 1997 summer. In 2001, he joined the Department of Electrical & Computer Engineering and Computer Science, University of Cincinnati, Ohio, USA. He was a visiting scholar with the Institute of Information Science, Academia Sinica, Taiwan, Republic of China, in 2002 summer. His research interests include VLSI design for testability, built-in self-testing, memory testing, high-performance circuit testing, MEMS testing and repairing, and low-power circuit design. He has published more than 100 papers and holds one patent (USA).
Dr. Jone served as a reviewer in these research areas in various technical journals and conferences. He is also listed in the Marquis Who's Who in the World (15th Edition, 1998, 2001). He also served on the program committee of VLSI Design/CAD Symposium (1993–1997, in Taiwan), was the General Chair of 1998 VLSI Design/CAD Symposium, served on the program committee of 1995, 1996, 2000 Asian Test Conference, 1995–1998 Asia and South Pacific Design Automation Conference, 1998 International Conference on Chip Technology, 2000 International Symposium on Defect and Fault Tolerance in VLSI Systems, and 2002, 2003 Great Lake Symposium on VLSI. He received the Best Thesis Award from The Chinese Institute of Electrical Engineering, (Republic of China), in 1981. He is a co-recipient of the 2003 IEEE Donald G. Fink Prize Paper Award. He is a senior member of IEEE and the IEEE Computer Society Test Technology Technical Committee.View more
CS Department, National Tsing Hua University, Hsinchu, Taiwan
Shih-Chieh Chang received the B.S. degree in Electrical Engineering from National Taiwan University in 1987 and the Ph.D. degree in Electrical Engineering from the University of California, Santa Barbara, in 1994. He worked at Synopsys, Inc., Mountain View, CA, from 1995 to 1996. He then joined the faculty at the Institute of Computer Science and Information Engineering, National Chung Cheng University, Taiwan from 1996 to 2001. He is now with the Department of Computer Science National Tsing Hua University Taiwan. His current research interests include VLSI logic synthesis, layout, and FPGA related applications. Dr. Chang received a Best Paper Award at the 1994 Design Automation Conference.
Shih-Chieh Chang received the B.S. degree in Electrical Engineering from National Taiwan University in 1987 and the Ph.D. degree in Electrical Engineering from the University of California, Santa Barbara, in 1994. He worked at Synopsys, Inc., Mountain View, CA, from 1995 to 1996. He then joined the faculty at the Institute of Computer Science and Information Engineering, National Chung Cheng University, Taiwan from 1996 to 2001. He is now with the Department of Computer Science National Tsing Hua University Taiwan. His current research interests include VLSI logic synthesis, layout, and FPGA related applications. Dr. Chang received a Best Paper Award at the 1994 Design Automation Conference.View more
ECECS Department, University of Cincinnati, OH, USA
Swaroop Ghosh received the B.E. degree in Electrical Engineering from the University of Roorkee (Now Indian Institute of Technology, Roorkee), India, in 2000. He worked at Mindtree Technologies Pvt. Ltd., Bangalore, India as a VLSI Design Engineer before joining the ECECS Department at University of Cincinnati in September 2002. His research interests are in the fields of digital testing and very large scale integrated circuit design. He is currently working on embedded core testing and signal integrity testing of high speed deep submicron interconnects.
Swaroop Ghosh received the B.E. degree in Electrical Engineering from the University of Roorkee (Now Indian Institute of Technology, Roorkee), India, in 2000. He worked at Mindtree Technologies Pvt. Ltd., Bangalore, India as a VLSI Design Engineer before joining the ECECS Department at University of Cincinnati in September 2002. His research interests are in the fields of digital testing and very large scale integrated circuit design. He is currently working on embedded core testing and signal integrity testing of high speed deep submicron interconnects.View more
