Abstract:
A 10 b 150 MHz multi-bit-per-stage single-channel CMOS pipelined ADC, incorporating temperature- and supply-insensitive CMOS references and improved gate-bootstrapping te...Show MoreMetadata
Abstract:
A 10 b 150 MHz multi-bit-per-stage single-channel CMOS pipelined ADC, incorporating temperature- and supply-insensitive CMOS references and improved gate-bootstrapping techniques for a wideband SHA, achieves a SNDR of 52 dB and SFDR of 65 dB at 150 MS/s. The ADC, fabricated in 0.18 /spl mu/m CMOS, occupies an active die area of 2.2 mm/sup 2/ and consumes 123 mW at 1.8 V.
Published in: 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.
Date of Conference: 13-13 February 2003
Date Added to IEEE Xplore: 26 February 2004
Print ISBN:0-7803-7707-9
Print ISSN: 0193-6530
Contents 