A 10 b 150 MS/s 123 mW 0.18 /spl mu/m CMOS pipelined ADC

A 10 b 150 MHz multi-bit-per-stage single-channel CMOS pipelined ADC, incorporating temperature- and supply-insensitive CMOS references and improved gate-bootstrapping techniques for a wideband SHA, achieves a SNDR of 52 dB and SFDR of 65 dB at 150 MS/s. The ADC, fabricated in 0.18 /spl mu/m CMOS, occupies an active die area of 2.2 mm/sup 2/ and consumes 123 mW at 1.8 V.

Applications such as high-definition video systems, personal mobile communication equipment, and high-speed digital wireless networks that make use of advanced CMOS VLSI, increasingly require high-resolution high-speed low power ADCs. Particularly, the ADCs for wired/wireless network applications and high-end imaging systems require 10b resolution at 150MS/s and need wideband sample-and-hold amplifiers (SHAs) to handle high frequency inputs. Conventional CMOS ADCs for high-speed applications have employed flash, folding, subranging, and pipelined architectures. The pipelined ADC architecture has commonly been employed to optimize speed, power dissipation, and chip area for applications with 10bits or more, at speeds exceeding 100MS/s [1]–[3].