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Quantitative characterization and process optimization of low-temperature bonded copper interconnects for 3-D integrated circuits | IEEE Conference Publication | IEEE Xplore

Quantitative characterization and process optimization of low-temperature bonded copper interconnects for 3-D integrated circuits


Abstract:

Three-dimensional (3-D) integrated circuits can be fabricated by bonding previously-processed device layers using metal-metal bonds that also serve as layer-to-layer inte...Show More

Abstract:

Three-dimensional (3-D) integrated circuits can be fabricated by bonding previously-processed device layers using metal-metal bonds that also serve as layer-to-layer interconnects. Bonded copper interconnect test structures were created by thermocompression bonding, and the bond toughness was measured using a four-point bend test. The effects of bonding temperature, chamber ambient and copper thickness on bond quality were evaluated to optimize the bonding process. A new copper surface cleaning method using glacial acetic acid was employed to obtain high toughness bonds(/spl sim/17 J/m/sup 2/) at low bonding temperatures (<300/spl deg/C).
Date of Conference: 04-04 June 2003
Date Added to IEEE Xplore: 11 August 2003
Print ISBN:0-7803-7797-4
Conference Location: Burlingame, CA, USA
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