A flexible design of a decision feedback equalizer and a novel CCK technique for wireless LAN systems

In the wireless mobile communication system, a decision feedback equalizer (DFE) to cancel the inter symbol interference (ISI) is required. This paper analyzes and implements the decision feedback equalizer and a novel CCK architecture of the receiver. All the filters are implemented using the finite impulse response (FIR) filter. The least mean square (LMS) algorithm with initial values is used for updating the coefficient as fast as it can be in the parallel DFE architecture. The area requirement of the novel CCK demodulator structure is about half of that of Fast Walsh Block structure, while their delay times are approximately the same. After synthesis, the total gate counts of the DFE and the CCK demodulator are 58624 and 9937, respectively. The power consumption of DFE is 25.087 mW operating under a 3.3 V supply voltage.

1. Introduction

The wireless LAN is aimed at grabbing information while the set moving all the time. Especially in recent days, the portable computer appends the capability of the wireless network communication, which is getting popularize rapidly. Figure 1 shows an example of the block diagram of the receiver architecture for the IEEE 802.11b wireless LAN system. It is important to integrate the benefits of WLAN MAC and PHY layers with 2.4GHz in radio frequency front-end. As a result of the 8-chip complementary code keying (CCK) modulation technique, the much higher data rate that means the chipping rate is 11MHz or 5.5MHz in Direct Sequence Spread Spectrum (DSSS) systems, can be achieved. However, an efficient CCK demodulation technique must be utilized. In this paper, a novel CCK demodulator structure is presented. Fig. 1.

The block diagram of BBP receiver