Active flow identifiers for scalable, QoS scheduling in 10-Gbps network processors

Most of the scheduling schemes proposed in the literature require complex calculations per flow and thus, their implementations are expensive, especially in terms of silicon area. Additionally, when these algorithms work at gigabit rates, they cannot support large numbers of network flows each with diverse rate requirements. Although nowadays it is technologically viable to implement such mechanisms that can provide QoS in hardware, this can be accomplished only if lower rates (couple of hundreds Mbits/sec at most) or small number of flows (few hundreds) are serviced by the scheduling mechanism. This paper introduces a novel scheduling scheme which can handle thousands of traffic flows, each with its own QoS parameters, at an aggregate rate of 10 Gbps. The hardware implementation of this algorithm requires only 17500 standard CMOS gates. This novel scheme is also very flexible and thus it can very easily be integrated in a large number of different high-performance networking Systems-on-Chip (SoCs).

1. INTRODUCTION

High-speed schedulers are an essential component of modem data networks. They are evolving into highly complex systems and are relying heavily on sophisticated traffic management mechanisms in order to achieve high resource utilization and support a bundle of services (i.e. best effort data delivery, guaranteed bandwidth services, voice, video. VPNs, and other qualityofservice (QoS) sensitive traffic). Scheduling is a function. related to the regulation of packet transmission times as a mean to provide prioritization and limited delay and jitter for QoS sensitive traffic¹

originally implemented in data switches but lately extended to all intermediate network nodes and processing elements

. It is therefore essential to provide scalable, flexible and cost-effective scheduler architectures to ensure optimum network performance for today's and tomorrow's switches and routers. In spite of the underlying CMOS technology continuing its progress to smaller geometries and higher speeds, novel architectural approaches are still needed in order to handle increasing requirements for QoS at multi-gigabit rates.