A 3 V 12b 100 MS/s CMOS D/A converter for high-speed system applications

This work describes a 3 V 12 bit 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for the 8 MSBs and a binary-weighted array for the 4 LSBs, trading-off linearity, power consumption, chip area, and glitch energy with this process. Low-glitch switch driving circuits are employed to improve linearity and dynamic performance. The DAC current sources are laid out separately from the current-cell switch matrix core block to reduce transient noise coupling. The prototype DAC is implemented in a 0.35 /spl mu/m n-well single-poly quad-metal CMOS technology and the measured DNL and INL are within /spl plusmn/0.75 LSB and /spl plusmn/1.73 LSB at 12 bit, respectively. The spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies an active die area of 2.2 mm/spl times/2.0 mm.