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Optimal interconnect circuits for VLSI | IEEE Conference Publication | IEEE Xplore

Optimal interconnect circuits for VLSI


Abstract:

THE PROPAGATION DELAY of interconnects is a major factor determining the performance of VLSI circuits, because the RC time constant of interconnects increases very rapidl...Show More

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Abstract:

THE PROPAGATION DELAY of interconnects is a major factor determining the performance of VLSI circuits, because the RC time constant of interconnects increases very rapidly as chip and interconnect dimensions are scaled aggressively. In this paper a simple model for interconnect time delay, including the effects of scaling transistor, interconnect and chip dimensions will be discussed. To reduce interconnect time delay, properly-scaled multilevel conductors, repeaters, cascaded drivers, and cascaded drivers as repeaters are presented. The delay model yields optimum cross sectional interconnect dimensions and driver/ repeater configurations that can reduce interconnect time delays by more than an order of magnitude
Date of Conference: 22-24 February 1984
Date Added to IEEE Xplore: 06 January 2003
Conference Location: San Francisco, CA, USA

First Page of the Article


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