3-D On-Chip Integration of GaN Power Devices on Power Delivery Network (PDN) With Direct Heat Spreading Layer Bonding for Heterogeneous 3-D (H3D) Stacked Systems

Heterogeneous 3-D (H3D) stacked systems offer numerous advantages for high-performance computing (HPC) and artificial intelligence/machine learning (AI/ML) applications. However, implementing H3D systems requires a re-designed power delivery network (PDN) for efficient power delivery in 3-D stacked systems and thermal management solutions. To develop an efficient PDN for the H3D system, a 3-D integrated on-chip power device is recommended. In this work, we demonstrate an H3D-integrated GaN power device on the PDN of a CMOS chip with direct heat-spreading layer bonding. The GaN power devices were designed to integrate both E-mode and D-mode with ${L}_{\text {G}}$ of $1.5~\mu $ m and ${L}_{\text {GD}}$ of $15~\mu $ m, and achieve a ${R}_{\scriptscriptstyle{\mathrm {on}}}$ of $22.3~\Omega $ mm and ${V}_{\text {BD}}$ of 137 V. These results surpass the limitation of silicon-based power devices. In addition, we experimentally demonstrated that direct heat spreading layer bonding effectively relaxed the thermal effect of H3D-integrated GaN power devices using a thermoreflectance microscopy (TRM) system for the first time. By introducing a heat spreading layer, the thermal resistance ( ${R}_{\text {TH}}$ ) of the GaN power device was reduced by 48.8% compared to GaN power devices without a heat spreading layer. These findings mark a substantial advancement in PDN technology, setting the stage for vertically integrated active PDNs that support efficient power delivery and effective thermal management in H3D stacked systems.

I. Introduction

The performance of the semiconductor chips has been improved through scaling and structural innovations of the transistors in the chip. However, the traditional methods for performance improvement are reaching their limits in terms of cost and physical constraints. To surpass these limitations, there is growing interest in 3-D integration. Three-dimensional integration stacks chips vertically with fine integration pitches, offering advantages of higher functionality, density, lower communication latency, efficient power dissipation, and application heterogeneity [1]. Particularly, these characteristics make heterogeneous 3-D (H3D) stacked systems well-suited for high-performance computing (HPC) and artificial intelligence/machine learning (AI/ML) applications, which require logic, processors, and various types of memory chips.