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Millisecond Pulsed Light Annealing for Improving Performance of Top-Gate Self-Aligned a-IGZO TFT | IEEE Journals & Magazine | IEEE Xplore

Millisecond Pulsed Light Annealing for Improving Performance of Top-Gate Self-Aligned a-IGZO TFT


Abstract:

The application of millisecond intense pulsed light (IPL) annealing to improve the electrical properties of top-gate self-aligned (TG-SA) amorphous indium gallium zinc ox...Show More

Abstract:

The application of millisecond intense pulsed light (IPL) annealing to improve the electrical properties of top-gate self-aligned (TG-SA) amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) was investigated. The IPL annealing with a pulse energy of 40 J/cm2 and a pulsewidth of 20 ms resulted in 53.7% increase in \mu _{\text {FE}} and a 128.4% improvement in {I}_{\text {on}} , compared to the unannealed devices. These improvements are attributed to the selective improvement of the specific contact resistivity ( \rho _{\text {c}} ) by the IPL annealing. In addition, positive bias stress (PBS) reliability and temperature-dependent I–V measurements show the improved stability in the IPL-annealed devices and the lower activation energy ( {E}_{\text {A}} ) for charge transport, indicating that the channel region would also have a lower defect density and barrier height for carrier transport.
Published in: IEEE Transactions on Electron Devices ( Volume: 72, Issue: 5, May 2025)
Page(s): 2399 - 2405
Date of Publication: 09 April 2025

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I. Introduction

Oxide semiconductors, particularly amorphous indium gallium zinc oxide (a-IGZO), have emerged as promising materials for advanced electronics, due to their unique properties [1]. These include low temperature processability, moderate electron field effect mobility (), good reliability, high uniformity, and ultralow off-state current [2]. These properties make the oxide semiconductors ideal for low-power electronic devices such as switching transistors in active-matrix displays [3], [4] and access transistors in dynamic random access memory [5], [6], [7]. In addition, the moderate electron mobility ensures efficient transport charge, while good reliability and high uniformity contribute to consistent performance across devices [8]. To optimize the performance of oxide semiconductor devices, the top-gate self-aligned (TG-SA) structure has emerged as the preferred architecture because of its minimal overlap between the gate and source/drain regions, which reduces the parasitic capacitance [9], [10]. This reduction not only increases the switching speed, but also minimizes energy loss, making TG-SA structures important for efficient and reliable device operation [11].

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