I. Introduction
Oxide semiconductors, particularly amorphous indium gallium zinc oxide (a-IGZO), have emerged as promising materials for advanced electronics, due to their unique properties [1]. These include low temperature processability, moderate electron field effect mobility (), good reliability, high uniformity, and ultralow off-state current [2]. These properties make the oxide semiconductors ideal for low-power electronic devices such as switching transistors in active-matrix displays [3], [4] and access transistors in dynamic random access memory [5], [6], [7]. In addition, the moderate electron mobility ensures efficient transport charge, while good reliability and high uniformity contribute to consistent performance across devices [8]. To optimize the performance of oxide semiconductor devices, the top-gate self-aligned (TG-SA) structure has emerged as the preferred architecture because of its minimal overlap between the gate and source/drain regions, which reduces the parasitic capacitance [9], [10]. This reduction not only increases the switching speed, but also minimizes energy loss, making TG-SA structures important for efficient and reliable device operation [11].