A 28-nm 239-bp/μJ Agile Pangenome Analysis Accelerator for Multi-Scheme Read Mapping

Recent advancements in deoxyribonucleic acid (DNA) sequencing have brought about a significant paradigm shift in genome analysis, moving from linear approaches to pangenome graphs. Pangenome analysis demands powerful computation capabilities to handle graph data structures, which are irregular and complex, as well as the flexibility to adapt to various algorithms and data types. This article presents the first silicon accelerator for pangenome read mapping. The 5.9-mm² 822-mW application-specific integrated circuit (ASIC) accelerator includes a dedicated graph mapping engine (GME) that leverages domain-specific characteristics to parallelize computations. It achieves a throughput of 151.8 Mbp/s and an energy efficiency of 239 bp/μJ in pangenome read mapping. Moreover, its dynamic reconfigurability and pipeline bubble hiding technique allow it to efficiently adapt to multiple mapping schemes with improved hardware utilization. It is backward compatible with conventional short-read mapping and offers up to 2.24× area efficiency and 3.65× energy efficiency compared to state-of-the-art short-read mapping silicon accelerators while maintaining an accuracy comparable with standard software packages.