Geometric Clustering for Hardware-Efficient Implementation of Chromatic Dispersion Compensation

Power efficiency is a major challenge in modern optical fiber communication, driving efforts to reduce the computational complexity of chromatic dispersion compensation (CDC) algorithms. While various reduction strategies exist, many lack hardware implementations to validate their practical benefits regarding energy efficiency and hardware resource usage. This paper analyzes the tap overlapping effect in CDC filters for coherent receivers, introduces in detail the Time-Domain Clustered Equalizer (TDCE) to leverage this effect, and presents the validation through FPGA implementation for fiber lengths up to 640 km. Furthermore, we introduce an innovative parallelization method, and evaluate the memory impact on energy efficiency, chip area, and resource utilization. A fair comparison is conducted against the state-of-the-art frequency-domain equalizer (FDE). Furthermore, we demonstrate that TDCE is compatible with machine learning optimization, enabling up to 33.3% complexity reduction. Our findings highlight that implementation strategies—such as parallelization and memory organization—are as crucial as computational complexity in determining hardware efficiency. Despite TDCE's higher theoretical computational complexity, its optimized hardware implementation achieves up to 70.7% energy savings and a 71.4% reduction in multiplier usage compared to FDE. These results emphasize that computational complexity alone is not a reliable predictor of energy efficiency and multiplier usage in CDC filters.