Abstract:
This work proposes a high-power harmonic oscillator topology that adopts a series LC resonant feedback network to minimize the effective parasitic capacitance of the osci...Show MoreMetadata
Abstract:
This work proposes a high-power harmonic oscillator topology that adopts a series LC resonant feedback network to minimize the effective parasitic capacitance of the oscillator at the fundamental frequency while increasing the output power at the second harmonic by enabling a larger transistor size and minimizing the common-mode output conductance. Implemented in the 28-nm CMOS technology, the proposed 270-GHz oscillator achieves a peak output power of -3.2 dBm, a peak dc-to-RF efficiency of 0.81% and phase noise values of -56.8, -84.68 and -90.12 dBc/Hz at 100 kHz, 1 MHz and 10 MHz offsets, respectively.
Published in: IEEE Transactions on Circuits and Systems II: Express Briefs ( Early Access )
Funding Agency:
School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Republic of Korea
Department of Electronic Engineering, Seoul National University of Science and Technology, Seoul, Republic of Korea
School of Electrical Engineering, Chungbuk National University, Cheong-ju, Republic of Korea
School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Republic of Korea
School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Republic of Korea
Department of Electronic Engineering, Seoul National University of Science and Technology, Seoul, Republic of Korea
School of Electrical Engineering, Chungbuk National University, Cheong-ju, Republic of Korea
School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Republic of Korea