Gate Stack Engineering for Top-tier Devices in Monolithic 3D integration using Laser Annealing

In this study, we propose an approach to relieve the mechanical stress in the gate stack of top-tier devices during the monolithic 3D (M3D) integration process. In the M3D process, selective laser annealing process has been actively adopted for the fabrication of top-tier devices in order to avoid possible adverse effects on pre-existing bottom-tier devices. However, the perpendicular irradiation direction during the laser annealing generates a vertical thermal gradient across the gate stack of top-tier MOS devices, resulting in unavoidable mechanical stress that is detrimental to device performance. In this work, we have demonstrated that inserting an Al₂O₃ layer in between the TiN gate electrode and the HfO₂ gate dielectric can reduce the mechanical stress in the gate stack. This approach can reduce the residual mechanical stress in the gate stack by approximately 67%, resulting in a ~ 49% reduction in interface state density (Dit) and a ~ 20% improvement in carrier mobility.