Foundational Techniques and Principles for VLSI Testing Using Machine Learning

With the advent of Very-Large-Scale Integration (VLSI), testing has turned out to be much more troublesome as their size develops. Effective as these traditional VLSI testing methods are in simplification, implementing when it comes to modern circuits teeming strewn with millions of components is suitable and this is where they often falter. Machine learning (ML), as a recent sibling in the family of curtain technologies has opened doors to innovative solutions that may improve VLSI testing, ranging from faster detection and lower fake p/f ratio causing masking costs. A systematic survey of existing methods, techniques and frameworks that utilize ML for VLSI testing is presented in this paper. The survey has encompassed a wide set of ML paradigms, many under the umbrella of supervised/unsupervised/reinforcement learning to study their relevance in different VLSI testing phases (e.g., for fault diagnosis/test pattern generation/design-for-testability considerations). Lastly, the paper discusses how ML frameworks have to be integrated into established VLSI testing workflows and what possible opportunities/trade-offs with current incorporation practices. Performance Metrics: It also aims to evaluate key performance metrics, such as the accuracy/efficiency of a method or its scalability that may be thoroughly analyzed for an ML-based VLSI testing practice. The survey also points out vital gaps in the existing research and suggests possible ways to fill in these gaps by focusing on maybe developing more scalable, explainable & universally applicable ML models for VLSI testing. In addition, by organizing the vast body of work in this area and providing insights into how different approaches have been employed towards achieving specific testing objectives, it is envisaged that researchers and practitioners working on VLSI test research using machine learning will find a useful resource for advancing their contributions.