A Scalable High-Voltage Gain DC/DC Converter With Reduced Voltage Stress for DC Microgrid Integration

The conventional quadratic boost converter produces a high voltage gain. However, it has drawbacks, like switch voltage stress equal to the output voltage of the converter. This research introduced a novel approach: a scalable high-voltage gain converter strategically designed to address the voltage stress experienced by the switch and achieve a noteworthy reduction. This voltage stress reduction is applicable to all the stages of the proposed converter. It is worth highlighting that the converter ensures continuous input current and is configured with a common input and output ground, further enhancing its practicality. This study delves into an exhaustive steady-state analysis covering both the continuous and discontinuous conduction modes and the nonideal model. Furthermore, a comprehensive comparative analysis is presented, pitting the design and performance of the proposed converter against their recent high-gain counterparts. To evaluate dynamic performance, a small signal model is created. To confirm the dynamic and steady-state performance, a prototype of the proposed converter configuration is fabricated and tested, achieving a 48- to 650-V conversion and delivering 500 W of output power.

SECTION I. Introduction

DC microgrid systems are progressively becoming prevalent within the present electric power scenario. Where, the seamless integration of renewable energy sources (RES), such as solar PV panels and fuel cells, mandates power electronics based converters. The utilization of high-voltage gain dc–dc converters is prominent due to the low output voltage profile of RES sources. While fundamental converter topologies, such as boost and buck–boost converters theoretically offer infinite voltage gain as the duty cycle approaches unity, their practicality is curbed by conduction losses stemming from inductors and switches due to their intrinsic parasitic resistance, consequently imposing limitations on the converter's efficiency. Moreover, a substantial challenge arises in the form of a notable voltage stress experienced by the switch—a stress that equals or exceeds the output voltage [1]. Motivated by these deliberations, the evolution of high voltage-gain converters has emerged as a dynamic and fervent domain of research, spurring a flurry of inventive dc–dc converter designs [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21].

Switched inductor (SI) converter [3], featuring a voltage gain of ${1+D}/{1-D}$, and switched capacitor (SC) converters [2], [4], exhibiting a voltage gain of ${2}/{1-D}$, have been meticulously examined for their enhanced voltage gain attributes, originating from the basis of the classical boost converter. However, their voltage gain potential remains bounded. The innovation of a voltage multiplier (VM) paradigm has been introduced to the SI topology, ushering in enhanced voltage gain as evidenced in [5] with a voltage gain of ${2N}/{1-D}$, and [6] with a voltage gain of ${2(1+D)}/{1-D}$. Here, the enhancement of voltage gain is dependent on the count of VM cells integrated within the converter. In another configuration [7], a combination of SI and SC elements provides a voltage gain of ${3+D}/{1-D}$, accompanied by voltage self-balancing across the switch. Further, the concept in [8] advances a voltage gain of ${5+D}/{1-D}$. It is imperative to note about voltage gain, however, that these arrangements lack a common ground junction linking the input and output ports. Addressing this gap, a configuration detailed in [9] provides a voltage gain of ${4}/{1-D}$, along with mitigated voltage stress across the switches; however, it is noteworthy that this solution necessitates the integration of 16 components.

Recent advancements have introduced quadratic gain converters [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], representing a strategic avenue to enhance both voltage gain and the overall performance of converter systems. Notably, the quadratic boost converter (QBC) featured in [10] stands out for its high voltage gain of ${1}/{(1-D)^{2}}$. Nevertheless, this achievement comes at the cost of imposing a voltage stress on the switch that parallels the converter's output voltage. The pursuit of enhanced QBC voltage gain is further exemplified in [11]. However, a lamentable oversight in its design is the absence of a concerted effort to establish a common ground between input and output ports. The progression toward enhancing QBC's voltage gain is meticulously chronicled throughout studies [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], often necessitating an increased component count to enhance voltage gain and mitigate stress on switches and diodes. Nonetheless, it is crucial to acknowledge that the voltage gain enhancements achieved in converters [12], [13] are rather marginal. Furthermore, converters, such as [14], [15], [17], [18] collectively exhibit a common drawback: the absence of a common ground connection between input and output ports. For converters in [19] and [20], a voltage gain of ${2}/{(1-D)^{2}}$ is achieved with a single switch. However, the drawback emerges in the form of this single switch conducting the entire circuit current, leading to escalated losses. To alleviate this concern [21], the innovative approach presents a solution: retaining the same voltage gain while employing two switches to distribute the current stress. An interesting finding is found in the converter in [16], which showcases an impressively high voltage gain of ${(3+D)}/{(1-D)^{2}}$ while concurrently mitigating voltage stress across its components. While converters in [16] and [21] attained remarkable high voltage gains, it is noteworthy that their full operational capacities are yet to be fully harnessed. Cubic voltage gain converters were documented in [20] and [23]. Specifically, the converter in [22] achieves a voltage gain of ${1}/{(1-D)^{3}}$, while the converter in [23] attains a gain of ${2}/{(1-D)^{3}}$. It is noteworthy that in the case of the converter in [22], the switch voltage stress is equal to the converter's output voltage. Conversely, the converter in [23] is associated with decreased voltage stress; however, this advantage comes at the expense of a higher component count. The applications of high gain converter were discussed in [24], [25], and [26]. In [24], a converter was reported for solar PV application. A multilevel converter was reported with high gain capability for solar PV in [25]. In [26], quadratic gain-based converters for fuel cell applications were discussed. This article introduces a scalable high-voltage gain dc–dc converter for $n$ stage (SHVGC$_{n}$). The proffered converter provides a superior voltage gain when juxtaposed with its quadratic boost counterparts and significantly mitigates voltage stress exerted on active components. Notably, the proposed converter stands out by its ability to provide a common ground for input to output alongside a modular structure facilitating the facile stacking of multiple switching stages to enhance output voltage gain. The application of the proposed converter in the dc microgrid is given in Fig. 1. The rest of this article is organized as follows. The configuration of the proposed converter, its operation, and the associated mathematical analysis are given in Section II. Section III provides a detailed analysis of the proposed converter. In Section IV, the discussion covers design, element selection, parasitic effects, and a comparison of the current topologies and the proposed converter. In addition, a small signal model for the controller is presented. To reinforce the theoretical analyses, Section VI presents the outcomes obtained from practical experiments conducted on the designed prototype. Finally, Section VII concludes this article.

Figure 1.

Application of proposed converter in dc microgrid.

SECTION II. Scalable High-Voltage Gain Converter

The power circuit schematic of the devised SHVGC$_{n}$ is illustrated in Fig. 2, depicting a sequence of interconnected multistages attached to a standard boost converter. The standard boost converter is comprised of fundamental components, namely inductor $L$, capacitor $C$, diode $D$, and switch $S$. The attached additional $n$ stages comprises a total of $n$ capacitors ($C_{1}, C_{2},{\ldots }, C_{n}$), an equivalent number of diodes ($D_{1}, D_{2},{\ldots }, D_{n}$), and inductors ($L_{1}, L_{2},{\ldots }, L_{n}$). Each individual stage is equipped with a dedicated switch, facilitating precise control over the switching mechanism within that stage. Notably, the extensible nature of the interconnected stages allows for seamless scalability to attain higher voltage gains. The addition of each stage necessitates the inclusion of a single capacitor, diode, inductor, and switch. The additional notable features of the proposed SHVGC$_{n}$ design are the continuous source current, reduced voltage across the components, and common ground between the input and output ports. The input voltage supply, denoted as $v_{\text{i}}$, establishes a direct connection to the standard boost converter stage of the proposed converter, with subsequent stages interconnected in a multistage manner. Within each stage, the inductors adhere to the principles of SIs, fostering parallel charging that leads to a reduction in inductor rating and dimensions. This, in turn, alleviates voltage stress on the switches. The subsequent section provides a comprehensive analysis of the proposed converter, considering the ideal attributes of all components.

Figure 2.

Proposed scalable high-voltage gain converter.

A. Continuous Conduction Mode (CCM)

The SHVGC$_{n}$ functions in this mode when the current flowing through the inductors remains continuous and, at any given moment, exceeds the magnitude of the output current. The voltage and current waveforms across and through the individual components are depicted in Fig. 3. During this mode, the operational behavior of the SHVGC$_{n}$ is divided into two states: State 1, where all switches are turned on (from time $T_{0}$ to $T_{1}$); and State 2, in which all switches are turned off(from time $T_{1}$ to $T_{2}$).

Figure 3.

Characteristics waveform of the SHVGC$_{n}$.

State 1- Time ($T_{0}$ to $T_{1}$): This operational state of the converter occurs when all switches are turned on. The corresponding equivalent circuit of the converter is elucidated in Fig. 4(a). Within this state, the entire array of diodes ($D$, $D_{1}$ to $D_{n}$) are subjected to reverse bias, facilitating the simultaneous charging of all inductors ($L$, $L_{1}$ to $L_{n}$) via the input voltage supply, denoted as “$v_{i}$,” combined with the associated capacitor voltages. During this state, the inductor $L$ is charging by voltage $v_{i}$, and the current flowing through switch $S$ is equivalent to the summation of inductors current, while diode $D$ blocks the voltage across capacitor $C$. In stage 1, the inductor $L_{1}$ is charging by voltage across capacitor $C$, and the current flowing through switch $S_{1}$ is equivalent to the difference of currents flowing through switch $S$ and inductor $L$. Meanwhile, the diode $D_{1}$ blocks the summation of voltages across the capacitor $C_{1}$ and inductor $L_{1}$. In stage 2, the inductor $L_{2}$ is charging by addition of voltages across capacitors $C$ and $C_{1}$, and the current flowing through switch $S_{2}$ is equivalent to difference of currents flowing through switch $S_{1}$ and inductor $L_{1}$. Concurrently, the diode $D_{2}$ blocks the summation of voltages across the capacitor $C_{2}$ and inductor $L_{2}$. Similarly, this operational behavior is consistently replicated across the remaining stages. Furthermore, the load $R$ is powered by energy stored in the capacitors. Consequently, a similar pattern is observed across each inductor, culminating in the generation of distinct voltages across each inductor \begin{align*} {\begin{cases}v_{L}=v_{i}&\\ v_{Lj}=\frac{1}{\left(1-D\right)^{j} } v_{i},\ \ &\text{where } j=1\ \text{to} \ n\end{cases}} \tag{1} \end{align*} where “$v_{L}$” represent the voltage across inductor $L$. The duty cycle is denoted by $D$ and the voltage across the inductor of stage $j$ is denoted as “$v_{Lj}$.” The current flowing through each capacitor is determined as follows: \begin{align*} {\begin{cases}i_{C}=i_{C1}-i_{L1};& i_{C1}=i_{C2}-i_{L2}\\ i_{Cj}=i_{Cj-1}+i_{Lj},&\text{where } j=2\ \text{to} \ n \end{cases}} \tag{2} \end{align*} where “$v_{o}$” represents the output voltage, “$i_{C}$,” “$i_{C1}$,” and “$i_{Cn}$” denote the currents through capacitors $C$, $C_{1}$, and $C_{n}$, respectively. Furthermore, the current through the capacitor and inductor of stage $j$ are denoted as “$i_{Cj}$” and “$i_{Lj}$.”

Figure 4.

Equivalent circuit of the SHVGC$_{n}$. (a) State 1. (b) State 2.

State 2- Time ($T_{1}$ to $T_{2}$): This operational state of the converter occurs when all switches are turned off. The equivalent circuit of the converter is elucidated in Fig. 4(b). Within this state, the entire array of diodes ($D$, $D_{1}$ to $D_{n}$) are subjected to forward bias, enabling the simultaneous discharging of all inductors ($L$, $L_{1}$ to $L_{n}$) and transfer the energy to connected corresponding capacitor. During this state, the inductor $L$ is in series with the input supply, transferring its energy to capacitor $C$ through diode $D$, while switch $S$ blocks the voltage across capacitor $C$. Likewise, in the interconnected stages, each inductor (from $L_{1}$ to $L_{n}$) transfers its energy to the corresponding capacitor (from $C_{1}$ to $C_{n}$) via its respective diode (from $D_{1}$ to $D_{n}$), while its corresponding switch (from $S_{1}$ to $S_{n}$) blocks the voltage across the respective capacitor (from $C_{1}$ to $C_{n}$). Furthermore, the load $R$ is powered by both the input supply and the energy stored in the inductors. The voltages across the inductors are \begin{align*} {\begin{cases}v_{L}=v_{i}-v_{C}&\\ v_{Lj}=-v_{Cj},&\text{where } j=1\ \text{to} \ n\ \end{cases}} \tag{3} \end{align*} where, “$v_{C}$” denotes the capacitor $C$ voltage, the voltage across the capacitor of stage $j$ is denoted as “$v_{Cj}$.” The current flowing through each capacitor is determined as follows: \begin{align*} {\begin{cases}i_{C}=i_{i}-\frac{v_{o}}{R} &\\ i_{Cj}=i_{Lj}-\frac{v_{o}}{R}, &\text{where } j=1\ \text{to} \ n.\end{cases}} \tag{4} \end{align*} We know that the average voltage across the inductor is zero. Therefore, applying this principle, we can derive the steady-state voltage across the capacitors as follows: \begin{align*} {\begin{cases}V_{C}=\frac{1}{1-D} V_{i}&\\ V_{Cj}=\frac{D}{\left(1-D\right)^{j} } V_{C},&\text{where } j=1\ to\ n.\end{cases}} \tag{5} \end{align*} The steady-state output voltage of SHVGC$_{n}$, denoted here as “$V_{o}$,” is equal to $V_{C} + V_{C1} + \cdots + V_{Cn}$. Therefore, based on (5), the steady-state output voltage can be determined as \begin{equation*} V_{o}=\frac{1}{\left(1-D\right)^{n+1} } V_{i}. \tag{6} \end{equation*}

B. Discontinuous Conduction Mode

During discontinuous conduction mode (DCM) operation, the proposed SHVGC$_{n}$ operates in three distinct states. The equivalent circuit for the first two states of DCM is identical to the equivalent circuit of the continuous conduction mode (CCM) for its first two states. However, the key distinction between the states of CCM and DCM lies in the behavior of inductors. In CCM, the current through inductor $L_{n}$ remains nonzero throughout the entire operational period, whereas in DCM, it reaches zero by the end of the second mode. These differences delineate the presence of these three distinct states within the DCM operation of the SHVGC$_{n}$.

For State 1: The operation of DCM is the same as that of CCM. The current through the inductor $L_{n}$ initiates from zero at the beginning and gradually reaches its maximum value by the end of this state. The ripple current in the inductors can be expressed as \begin{equation*} \Delta I_{Ln}=\frac{V_{i}}{\left(1-D\right)^{n} L_{n}} \text{DT} \tag{7} \end{equation*} where $T$ denotes the switching time for a single cycle.

For State 2: The operation of DCM is the same as that of CCM. The current through the inductor $L_{n}$ initiates from the maximum value at the beginning and gradually reaches zero value by the end of this state. The ripple current in the inductors is \begin{equation*} \Delta I_{Ln}=\left[ V_{o}-\frac{V_{i}}{\left(1-D\right)^{n} } \right] \frac{D_{x}T}{L_{n}}. \tag{8} \end{equation*} Here, $D_{x}T$ signifies the duration of state 2 within a single switching cycle. When the time reaches $(D+D_{x})T$, the current in inductor $L_{n}$ i.e $i_{Ln}$, reaches zero, marking the end of state 2.

For State 3 (DCM): In this state, the current through the inductor remains at zero. As a result, the energy stored in inductor $L_{n}$ is zero, leading to $\Delta I_{L_{n}}=0$, and the current through diode $D_{n}$ is also zero. All the capacitors supply energy to the load $R$. Utilizing (7) and (8), the value of $D_{x}$ can be ascertained as \begin{equation*} D_{x}=\frac{V_{i}D}{V_{o}\left(1-D\right)^{n} -V_{i}}. \tag{9} \end{equation*} The average current through the capacitor $i_{Cn}$ is expressed as \begin{equation*} I_{Cn}^{\text{avg}}=\frac{\Delta I_{Ln}D_{x}}{2} -I_{o}^{\text{avg}}. \tag{10} \end{equation*} We know that the average current through any capacitor is zero. Utilizing this insight and substituting the expression of $\Delta I_{Ln}$ from (7) and $D_{x}$ from (9) into (10), the resulting expression is as \begin{equation*} \frac{V_{i}\text{DT}}{2\left(1-D\right)^{n} L_{n}} \left[ \frac{V_{i}D}{V_{o}\left(1-D\right)^{n} -V_{i}} \right] =\frac{V_{o}}{R}. \tag{11} \end{equation*} Using (11), the output voltage in DCM mode ($V_{o,\text{dcm}}$) is \begin{equation*} V_{o,\text{dcm}}=\left(\frac{1}{2} \pm \sqrt{\frac{1}{4} +\frac{D^{2}}{2\xi _{Ln} } } \right) \left(\frac{1}{1-D} \right) V_{i} \tag{12} \end{equation*} where $\xi _{Ln}$ represents the normalized time constant for inductors $L_{n}$, and its value is equal to ${L_{n}f}/{R}$. Consequently, the fluctuation in $\xi _{Ln}$ is contingent on the values of $L_{n}$, $f$, and $R$. In the scenario where the proposed converter is precisely operated at the boundary of CCM and DCM, then the output voltage of CCM ($V_{o}$) and DCM ($V_{o},\text{dcm}$) is the same. Thus, by employing (6) and (12), the normalized time constant at the boundary for the inductor $L_{n}$, denoted as $\xi _{Ln,B}$, is deduced as follows: \begin{equation*} \xi _{Ln,B} =\frac{D^{2}}{2} \left[ \frac{\left(1-D\right)^{2n} }{1-\left(1-D\right)^{n} } \right]. \tag{13} \end{equation*} Equation (13) is evident that $\xi _{Ln,B}$ depends on both $D$ and $n$. Consequently, Fig. 5 depicting how $\xi _{Ln,B}$ changes with respect to both $D$ and $n$. It is imperative to ensure that the components are chosen in a manner that guarantees $\xi _{Ln,B} \leq \xi _{Ln}$, thereby ensuring the CCM operation of the converter.

Figure 5.

Plots of $\xi _{Ln,B}$ versus $D$ of SHVGC$_{n}$ for (a) $n$=1, (b) $n$=2, and (c) $n$=3.

SECTION III. Stress Analysis of SHVGC$_{n}$

In this section, the expressions for voltage and current are presented where the variable $j$ serving as a distinguishing identifier for each specific stage and its value ranging from 1 to $n$. The expressions for the average, peak, and root mean square (rms) values of the current in the inductors are as follows: \begin{align*} \begin{array}{ll}I^{\text{avg}}_{L}=\frac{I^{\text{avg}}_{o}}{\left(1-D\right)^{n+1} } \; &I^{\text{avg}}_{Lj}=\frac{I^{\text{avg}}_{o}}{\left(1-D\right)^{n-(j-1)} } \end{array} \tag{14}\\ {\begin{cases}I^{pk}_{L}=\frac{I^{\text{avg}}_{o}}{\left(1-D\right)^{n+1} } +\frac{V_{i}\text{DT}}{2L} &\\ I^{pk}_{Lj}=\frac{I^{\text{avg}}_{o}}{\left(1-D\right)^{n-(j-1)} } +\frac{V_{i}\text{DT}}{2L_{j}\left(1-D\right)^{j} } & \end{cases}} \tag{15}\\ {\begin{cases}I^{\text{rms}}_{L}=\sqrt{\frac{\left(I^{\text{avg}}_{o}\right)^{2} }{\left(1-D\right)^{2(n+1)} } +\frac{1}{12} \left(\frac{V_{i}\text{DT}}{L} \right)^{2} } &\\ I^{\text{rms}}_{Lj}=\sqrt{\frac{\left(I^{\text{avg}}_{o}\right)^{2} }{\left(1-D\right)^{2n-2(j-1)} } +\frac{1}{12\left(1-D\right)^{2j} } \left(\frac{V_{i}\text{DT}}{L_{j}} \right)^{2}. } &\end{cases}} \tag{16} \end{align*} The expressions for the average, peak, and rms values of the current in the switches are as follows: \begin{align*} & {\begin{cases}I^{\text{avg}}_{S}=\frac{I^{\text{avg}}_{o}\left(1-\left(1-D\right)^{n+1} \right)}{\left(1-D\right)^{n+1} } &\\ I^{\text{avg}}_{Sj}=\frac{I^{\text{avg}}_{o}\left(1-\left(1-D\right)^{n-\left(j-1\right) } \right)}{\left(1-D\right)^{n-\left(j-1\right) } } &\end{cases}} \tag{17}\\ &{\begin{cases}I^{pk}_{S}=\frac{I^{\text{avg}}_{o}\left(1-\left(1-D\right)^{n+1} \right) }{D\left(1-D\right)^{n+1} } +\frac{V_{i}\text{DT}}{2} \left(\frac{1}{L} +\sum ^{n}_{p=1} \frac{1}{L_{p}\left(1-D\right)^{p} } \right) &\\ I^{pk}_{Sj}=\frac{I^{\text{avg}}_{o}\left(1-\left(1-D\right)^{n-\left(j-1\right) } \right) }{D\left(1-D\right)^{n-\left(j-1\right) } } +\frac{V_{i}\text{DT}}{2} \left(\sum ^{n}_{p=j} \frac{1}{L_{p}\left(1-D\right)^{p} } \right) &\end{cases}} \tag{18}\\ &{\begin{cases}I^{\text{rms}}_{S}=\sqrt{\frac{\left(I^{\text{avg}}_{o}\left(1-\left(1-D\right)^{n+1} \right) \right)^{2} }{D\left(1-D\right)^{2n+2} } +\frac{D}{12} \left(\spadesuit \right)^{2} } &\\ \spadesuit =\frac{V_{i}\text{DT}}{L} +\sum ^{n}_{p=1} \frac{V_{i}\text{DT}}{L_{p}\left(1-D\right)^{p} } &\\ I^{\text{rms}}_{Sj}=\sqrt{\frac{\left(I^{\text{avg}}_{o}\left(1-\left(1-D\right)^{n-\left(j-1\right) } \right) \right)^{2} }{D\left(1-D\right)^{2n-2\left(j-1\right) } } +\frac{D}{12} \left(\sum ^{n}_{p=j} \frac{V_{i}\text{DT}}{L_{p}\left(1-D\right)^{p} } \right)^{2} }. &\end{cases}} \tag{19} \end{align*} The expressions for the average, peak, and rms values of the current in the diodes are as follows: \begin{align*} &\begin{array}{ll}I^{\text{avg}}_{D}=\frac{I^{\text{avg}}_{o}}{\left(1-D\right)^{n} } \; &I^{\text{avg}}_{Dj}=\frac{I^{\text{avg}}_{o}}{\left(1-D\right)^{n-j-1} } \end{array} \tag{20}\\ &{\begin{cases}I^{pk}_{D}=\frac{I^{\text{avg}}_{o}}{\left(1-D\right)^{n+1} } +\frac{V_{i}\text{DT}}{2L} &\\ I^{pk}_{Dj}=\frac{I^{\text{avg}}_{o}}{\left(1-D\right)^{n-(j-1)} } +\frac{V_{i}\text{DT}}{2L_{j}\left(1-D\right)^{j} } &\end{cases}} \tag{21}\\ &{\begin{cases}I^{\text{rms}}_{D}=\sqrt{\frac{\left(I^{\text{avg}}_{o}\right)^{2} (1-D)}{\left(1-D\right)^{2(n+1)} } +\frac{(1-D)}{12} \left(\frac{V_{i}\text{DT}}{L} \right)^{2} } &\\ I^{\text{rms}}_{Dj}=\sqrt{\frac{\left(I^{\text{avg}}_{o}\right)^{2} (1-D)}{\left(1-D\right)^{2n-2(j-1)} } +\frac{1-D}{12} \left(\sum ^{n}_{p=j} \frac{V_{i}\text{DT}}{L_{p}\left(1-D\right)^{p} } \right)^{2} }. &\end{cases}} \tag{22} \end{align*} The average voltage across an inductor is generally zero. As a result, $I^{\text{avg}}_{C}$ and $I^{\text{avg}}_{Cj}$ (where $j=1$ to $n$), are zero. The peak voltage across capacitors during charging and discharging are, \begin{align*} {\begin{cases}\text{During Discharging} &\\ I^{pk}_{C}=-I_{o}\left(\frac{1-\left(1-D\right)^{n+1} }{D\left(1-D\right)^{n} } \right); \ & I^{pk}_{Cj}=-I_{o}\left(\frac{1-\left(1-D\right)^{n-j+1} }{D\left(1-D\right)^{n-j} } \right) \\ \text{During Charging} &\\ I^{pk}_{C}=I_{o}\left(\frac{1-\left(1-D\right)^{n+1} }{\left(1-D\right)^{n+1} } \right); \ & I^{pk}_{Cj}=I_{o}\left(\frac{1-\left(1-D\right)^{n-j+1} }{\left(1-D\right)^{n-j+1} } \right). \end{cases}} \tag{23} \end{align*} The rms value of current flowing in capacitors are determined as \begin{align*} {\begin{cases}I_{C}^{\text{rms}}=I_{o}\left(\frac{1-\left(1-D\right)^{n+1} }{\left(1-D\right)^{n+0.5} \sqrt{D} } \right); & I^{\text{rms}}_{Cj}=I_{o}\left(\frac{1-\left(1-D\right)^{n-j+1} }{\left(1-D\right)^{n-j+0.5} \sqrt{D} } \right). \end{cases}} \tag{24} \end{align*} The average voltage across an inductor is generally zero. As a result, $V^{\text{avg}}_{L}$ and $V^{\text{avg}}_{Lj}$ (where $j=1$ to $n$), are zero. The peak voltage across an inductor during charging and discharging are \begin{align*} {\begin{cases}V^{pk}_{L}=V_{i},\ V^{pk}_{Lj}=\frac{V_{i}}{(1-D)^{j}} &\text{During Charging} \\ V^{pk}_{L}=\frac{-\text{DV}_{i}}{1-D}, \ V^{pk}_{Lj}=\frac{-\text{DV}_{i}}{(1-D)^{j+1}} &\text{During Discharging.} \end{cases}} \tag{25} \end{align*} The rms value of voltage across an inductors is expressed as \begin{align*} \begin{array}{ll}V^{\text{rms}}_{L}=V_{i}\sqrt{\frac{D}{1-D} } \; &V^{\text{rms}}_{Lj}=\frac{V_{i}}{(1-D)^{j}} \sqrt{\frac{D}{1-D} }. \end{array} \tag{26} \end{align*} The expressions for the average, peak, and rms values of the voltage across switches are as follows: \begin{gather*} V^{\text{avg}}_{S}=V_{i}; \quad V^{\text{avg}}_{Sj}=\frac{\text{DV}_{i}}{(1-D)^{j}} \tag{27}\\ V^{pk}_{S}=\frac{V_{i}}{1-D}; \quad V^{pk}_{Sj}=\frac{\text{DV}_{i}}{(1-D)^{j+1}} \tag{28}\\ V^{\text{rms}}_{S}=\frac{V_{i}}{\sqrt{1-D} }; \quad V^{\text{rms}}_{Sj}=\frac{D\sqrt{1-D} V_{i}}{(1-D)^{j+1}}. \tag{29} \end{gather*} The expressions for the average, peak, and rms values of the voltage across diodes are as follows: \begin{align*} V^{\text{avg}}_{D}=\frac{\text{D V}_{i}}{1-D}; \quad V^{\text{avg}}_{Dj}=\frac{\text{DV}_{i}}{(1-D)^{j+1}} \tag{30}\\ V^{pk}_{D}=\frac{-V_{i}}{1-D}; \quad V^{pk}_{Dj}=\frac{-V_{i}}{(1-D)^{j+1}} \tag{31}\\ V^{\text{rms}}_{D}=\frac{\sqrt{D} V_{i}}{1-D}; \quad V^{\text{rms}}_{Dj}=\frac{\sqrt{D} V_{i}}{(1-D)^{j+1}}. \tag{32} \end{align*} The voltage across the capacitors are determined as \begin{align*} \begin{array}{ll}V_{C}=\frac{V_{i}}{1-D}; &V_{Cj}=\frac{\text{DV}_{i}}{(1-D)^{j+1}}. \end{array} \tag{33} \end{align*}

SECTION IV. Design and Comparison

The proposed converter components are designed by taking the worst-case scenario into account to meet the specifications in CCM, an $V_{i}$ of 44–54V (typical $ V_{i}=48 V$) and an $V_{o}$ of 650 V to deliver an $P_{o}$ of 500 W while operating at a frequency ($f$) of 50 kHz. The selected elements and values are given in Table 1. To optimize the number of components, the maximum control limit of the duty cycle ($D_{\text{max}}$) is set to $D\leq 0.8$, and the necessary number of stages for the provided input and output specifications is determined as \begin{align*} n & >\frac{\log \left(V_{i,\text{min}}\right) -\log \left(V_{o}\right) }{\log (1-D)} -1=\frac{\log (44) -\log (650) }{\log (1-0.8)} -1\\ &=0.67. \tag{34} \end{align*} Equation (34) is employed to ascertain that the proposed SHVGC$_{n}$, specifically with $n=1$, is indeed sufficient to achieve the desired voltage gain. So, the reaming analysis of this article is carried out for SHVGC$_{1}$, where the number of stages is 1 ($n=1$). To ascertain the actual required duty cycle $D$, the minimum input voltage is used because it yields the highest switch current. The inclusion of efficiency in the duty cycle calculation is essential, considering that the converter is responsible for delivering the dissipated energy \begin{align*} D&=1-10^{\left(\frac{\log \left(V_{i,\text{min}}\right) +\log \left(\eta \right) -\log \left(V_{o}\right) }{n+1} \right) }\\ &=1-10^{\left(\frac{\log (48) +\log (0.9) -\log (650) }{2} \right) }=0.753. \tag{35} \end{align*} A reliable estimate for the inductor ripple current falls within the range of 20%–40% of the average current. Therefore, the critical inductor current rating is calculated by considering its ripple current 25% of its current rating as follows: \begin{align*} {\begin{cases}I^{}_{L,c}=\frac{I^{\text{avg}}_{o}}{\left(1-D\right)^{2} 0.875} =\frac{0.77}{(1-0.742)^{2}0.875} =14.42\ A&\\ I_{L1,c}=\frac{I^{\text{avg}}_{o}}{\left(1-D\right) 0.875} =\frac{0.77}{(1-0.742)0.875} =3.56\ A.&\end{cases}} \tag{36} \end{align*} The critical inductance levels of inductors are calculated as \begin{align*} {\begin{cases}L_{c}=\ \frac{V_{i,\text{min}}D}{f\left(0.25\times I_{L,c}\right) } =183.83\ \mu H&\\ L_{c1}=\ \frac{V_{i,\text{min}}D}{f\left(1-D\right) \left(0.25\times I_{L1,c}\right) } =3014.7\ \mu H.&\end{cases}} \tag{37} \end{align*} The inductor ratings for the SHVGC$_{1}$ must be higher than the calculated values in (36) and (37). Consequently, for the hardware prototype, inductors with values of $L=0.2\ \text{mH}$, 20A and $L_{1}=4\ \text{mH}$, 5 A have been chosen. Core selection: To select the particular core, the energy present in the inductor is calculated as $LI^{2}$ ($\text{mH}-A^{2}$). The first inductor $L$ of the proposed converter is considered for sample calculation. From (36) and (37) the current of the inductor is 14.42 A and the inductor $L$ value is 0.2 mH. From this, the energy present in the inductor is calculated as 41.58 $\text{mH}-A^{2}$. From the magnetics powder core catalog under core selector charts as per the energy in the inductor of 41.58 $\text{mH}-A^{2}$, 77721 core is selected. Based on the core selection, the number of turns required is calculated by using the standard formula of $N = \text{Sqrt}(L*10^{3}/A_{L})$. Wire optimization: In this calculation, current density $J$ is considered as 5 $\text{A/mm}^{2}$ . The current of the inductor is 14.42 A. So, the wire area is calculated as 14.42 $A$/ 5 $\text{A/mm}^{2}$ =2.884 $\text{mm}^{2}$, which is equal to 0.02884 $\text{cm}^{2}$. From the wire table, 13 AWG wire size is selected as per the wire area calculation to design the inductor.

TABLE 1 Components Selection for SHVGC$_{1}$

The critical capacitor voltage rating and output voltage are calculated by considering its ripple voltage 1% of its voltage \begin{align*} V_{C,c}&=\frac{V_{i}}{\left(1-D\right) 0.95} =204.55\ V\\ V_{C1,c}&=(V_{o}+0.5\Delta V_{o})-V_{C,c}=448.7\ V. \tag{38} \end{align*} The critical capacitance levels of capacitors are calculated as \begin{align*} {\begin{cases}C_{c}=\ \frac{I_{o}\left(2-D\right) D}{\left(1-D\right) \left(\Delta V_{C,c}\right) f} =28.69\ \mu F&\\ C_{1,c}=\ \frac{I_{o}D}{\left(\Delta V_{C1,c}\right) f} =2.58\ \mu F.&\end{cases}} \tag{39} \end{align*} The capacitor ratings for the SHVGC$_{1}$ should be higher than the calculated values in (38) and (39). For the hardware prototype, capacitors with values of $C=100\ \mu F$, 450 V, and $C_{1}=100\ \mu F$, 450 V (two capacitors connected in series to meet the required voltage rating) have been selected. The critical current rating of the switches is calculated as \begin{align*} {\begin{cases}I^{}_{S,c}=I^{}_{L,c}+I^{}_{L1,c}=17.98\ A&\\ I_{S1,c}=I^{}_{L1,c}=3.56\ A.&\end{cases}} \tag{40} \end{align*} The critical voltage rating of the switches is calculated as \begin{align*} {\begin{cases}V^{}_{S,c}=V^{}_{C,c}=204.55\ V&\\ V_{S1,c}=V_{o}+0.5\Delta V_{o}-V^{}_{S,c}=448.7\ V.&\end{cases}} \tag{41} \end{align*} The critical current rating of the diodes is calculated as \begin{align*} {\begin{cases}I^{}_{D,c}=I^{}_{L,c}=14.42\ A&\\ I_{D1,c}=I^{}_{L1,c}=3.56\ A.&\end{cases}} \tag{42} \end{align*} The peak inverse voltage rating of the diodes is, \begin{align*} {\begin{cases}V^{}_{D,c}=-V^{}_{C,c}=-204.55\ V&\\ V_{D1,c}=-(V_{o}+0.5\Delta V_{o})=-653.25\ V.&\end{cases}} \tag{43} \end{align*}

A. Parasitic Effect of Selected Elements on Voltage Gain

Owing to the existence of parasitic components, the output voltage experiences deviations from the ideal voltage. To evaluate the influence of these parasitic elements, the equivalent winding resistances of inductors $L$ and $L_{1}$ are represented as “$r_{L}$ = 20 m$\Omega$.” An equivalent series resistance for capacitors $C$ and $C_{j}$ are introduced, denoting them as “$r_{C}$ = 10 m$\Omega$.” The on-state series resistances, denoted as “$r_{S}$ = 25 m$\Omega$,” are taken into account for switches $S$ and $S_{1}$. And, the switches $t_{\text{on}}+t_{\text{off}}$ = 63 ns. Furthermore, the on-state resistances, represented as “$r_{D}$ = 30 m$\Omega$,” are incorporated for diodes $D$ and $D_{1}$, respectively, in series with their respective barrier voltages, namely, $V_{\text{FD}}$ = 0.7 V. \begin{align*} V_{o}=\frac{V_{in}-\left(\frac{2-D}{1-D} \right) V_{\text{FD}}}{\left(1-D\right)^{2} +a\frac{r_{L}}{R} +b\frac{r_{C}}{R} +c\frac{r_{S}}{R} +p\frac{r_{d}}{R} } \tag{44} \end{align*} where, $a=\frac{2-2D+D^{2}}{(1-D)^{4} }$, $b=\frac{5D-6D^{2}+2D^{3}}{(1-D)^{3} }$, $c=\frac{4D-4D^{2}+D^{3}}{(1-D)^{4} }$, and $p=\frac{D+(1-D)^{3} }{(1-D)^{4} }$. The power losses in inductors ($P^{l}_{L}$) and capacitors ($P^{l}_{C}$), in switches due to conduction and switching ($P^{l}_{S,c}$ and $P^{l}_{S,sw}$), in diodes due to conduction and forward voltage ($P^{l}_{D,c}$ and $P^{l}_{D,vfd}$) are calculated by considering the above parasitic values for 500-W load power and output voltage of 650 V from 48-V input voltage as, \begin{align*} & P^{l}_{L}=\sum ^{2}_{i=1} i_{Li}^{2} r_{L}=\frac{2-2D+D^{2}}{(1-D)^{4} } i^{2}_{o}r_{L}=2.33\ W.\\ & P^{l}_{C}=\sum ^{2}_{i=1} (i^{\text{rms}}_{Ci})^{2} r_{C}=\frac{5D-6D^{2}+2D^{3}}{(1-D)^{4} } i^{2}_{o}r_{C}=0.36\ W.\\ & P^{l}_{S,c}=\sum ^{2}_{i=1} (i^{\text{rms}}_{Si})^{2} r_{S}=\frac{5D-6D^{2}+2D^{3}}{(1-D)^{4} } i^{2}_{o}r_{S}=3.34\ W.\\ & P^{l}_{S,sw}=\frac{1}{2} \sum ^{2}_{i=1} (V_{Si}i^{\text{avg}}_{Si}) f(t_{on}+t_{\text{off}})=4.23\ W.\\ & P^{l}_{D,c}=\sum ^{2}_{i=1}(i^{\text{rms}}_{Di})^{2} r_{d}=\frac{2-2D+D^{2}}{(1-D)^{3}}i^{2}_{o}r_{d}=0.94\ W.\\ & P^{l}_{D,vfd}=\sum ^{2}_{i=1} i^{\text{avg}}_{Di}V_{fd}=\frac{2-D}{1-D} V_{FD}i_{o}=2.51\ W.\\ & \text{Efficiency}=\frac{500W}{500 W+ \text{losses}}= 97.33\% \end{align*}

B. Performance Comparison With Similar Converters

The losses of the QBC [10] are computed. The comparison between the SHVGC$_{1}$ and QBC [10] is visually depicted through plots of output voltage against duty cycle and efficiency against power, as illustrated in Fig. 6. The plot clearly illustrates that the SHVGC$_{1}$ provides an output voltage of roughly 635.6 V at 72.9% duty ratio, whereas the QBC [10] produces 618.5 V. Moreover, the efficiency profile reveals that the SHVGC$_{1}$ exhibits superior performance compared to the conventional QBC [10]. The breakdown analysis of losses for both converters carried out for 500 W is illustrated in Fig. 6(c). Notably, the changes made to the QBC [10] circuit have led to a substantial reduction in semiconductor device losses. Fig. 6(d) provides a comparison of losses between the switch $S$ and additional diode $D_{3}$ of the QBC (replaced by $S_{1}$) in the proposed converter. The combined loss of diode $D_{3}$ and switch S in the QBC [10] amounts to 20.80 W, whereas in the SHVGC$_{1}$, the corresponding loss is reduced significantly to just 7.56 W (comprising losses from $S$ and $S_{1}$). As a result, the performance of the SHVGC$_{1}$ is notably enhanced in comparison to the QBC [10], with an efficiency improvement 2%. To estimate the converter's cost, it is essential to determine the cost of its components. The cost of the components depends on the voltage stress and current stress of the components. Notably, the cost of the components is increasing in a parabolic way with component ratings, i.e., high-rating components mean higher cost. Since the involvement of the (inductors and capacitors) in terms of rating is the same for the QBC [10] and proposed converter. However, they differ in switches and diodes' voltage and current stresses. To estimate the cost, it is essential to understand the total voltage stress and total current stress of switches and diodes for both converters. However, the cost of the converter depends on the tradeoff between the selection of the switches and didoes. Fig. 6(e) and (f) show the total current stress and total voltage stress switches and diodes. Because of this lower voltage and current stress capability, the proposed converter is also suitable for high-power operations. Along with the above advantages, the following are the additional advantages of the proposed converter.

1. The proposed converter is scalable to n-stage. In each stage of extension, the proposed converter needs only four components (1-switch, 1-diode, 1-capacitor, and 1-inductor).

2. The proposed converter source current is continuous, which is more suitable for integrating all types of RESs, such as fuel cells and Solar PV. This future is presented for all stages of the proposed converter.

3. The proposed converter also has common ground capability and helps minimize electromagnetic interference issues by providing a unified return path for currents. This future is also presented for all stages of the proposed converter.

Figure 6.

Comparison of QBC [10] and proposed SHVGC$_{1}$ converter. (a) Parasitic output voltage. (b) Output power versus efficiency. (c) and (d) Loss Breakdown. (e) Total switches and diodes current stress. (f) Total switches and diodes voltage stress.

A thorough assessment of the SHVGC$_{1}$’s with existing other similar converters is done, as outlined in Table 2. The tabulated data in Table 2 illuminates various facets, including the number of components, voltage gain, and the voltage and current stresses experienced by these components. In a study by [10], the QBC was detailed with eight components, showcasing commendable voltage gain. However, it was noted for its elevated switch voltage stress equal to the output voltage of the converter. Subsequent efforts to enhance the voltage gain, as documented in [12], while successful, did not ameliorate the switch's voltage stress, which remained consistent with the configuration in [10]. This persistent high voltage stress on the switch engenders increased switching losses, thereby compromising the efficiency of the converter. Noteworthy alternatives, as identified in [13], [15], and [16], employ a dual-switch configuration to achieve high voltage gain while concurrently mitigating stress on the components, leading to enhanced efficiency. This strategic use of dual switches contributes to a reduction in overall stress, thereby addressing the challenges associated with high voltage stress encountered in converter designs [10], [12]. However, the increased number of components in these converters contributes to lower power density and higher costs. On the contrary, the authors in [14] and [19] introduced converters that achieve high voltage gain utilizing a single switch. However, the entire circuit current flowing through the high voltage-rated single switch, where a high voltage rating implies elevated on-state resistance, leads to reduced efficiency. Another converter, detailed in [21], attains a higher voltage gain through a dual-switch setup, accompanied by lower voltage and current stress on the switches, thereby improving overall efficiency. Nevertheless, despite this efficiency enhancement, the total number of components used exceeds that of the QBC detailed in [10]. In response to these considerations, a newly SHVGC$_{1}$ (when $n =1$) mirrors the voltage gain and component count of the QBC [10]. The use of low-voltage-rated switches in the converter results in a decrease in the on-state resistance and voltage stress experienced by the switches, leading to a corresponding reduction in switching losses. Consequently, this contributes to an enhancement in the overall efficiency of the converter. In Fig. 7(a), the relationship between parasitic output voltage and efficiency is illustrated for an input voltage of 48 V and power output of 500 W, with variations in the duty ratio. The efficiency of all the converters reported in Table 2 carried out for the specifications of 500-W load power and output voltage of 650 V from 48-V input voltage and the parasitic values considered as $r_{L}$ = 20 m$\Omega$, $r_{C}$ = 10 m$\Omega$, $r_{S}$ = 25 m$\Omega$, $t_{\text{on}}+t_{\text{off}}$ = 63 ns, $r_{D}$ = 30 m$\Omega$, and $V_{\text{FD}}$ = 0.7V. The proposed designed SHVGC$_{1}$ demonstrates superior efficiency compared to conventional converters, with the exception of converter [15]. Notably, the converter in [15] achieves high efficiency but employs 16 components and lacks a common ground between the input and output ports. Conversely, converters in [13], [16], and [21] exhibit efficiency levels comparable to the SHVGC$_{1}$, especially at higher output voltages. However, it is worth noting that these alternative converters utilize a greater number of components compared to the proposed design. In Fig. 7(b), a graph has been depicted to clear the converter's efficiency. Notably, the SHVGC$_{1}$ demonstrates superior efficiency within the duty ratio range of 65%–76%. Utilizing this duty ratio for the converter to generate the required output voltage ensures that the converter's capabilities and switches utilization are maximally harnessed. Switch maximum voltage stress of the SHVGC$_{1}$ and state-of-the-art converters are plotted and shown in Fig. 8. The SHVGC$_{1}$ maximum voltage stress of the switch is less than the converters reported in [10] and [12]. The number of components used in the SHVGC$_{1}$ and converter [10] are equal, whereas it is lower when compared to the converter [12]. The converters reported in [13], [14], [15], [16], [19], [20], and [21] use more components than the SHVGC$_{1}$, and utilization of more components helps the reduction in the voltage stress of the switches.

TABLE 2 Comparison of Proposed SHVGC$_{1}$ Converters With Similar Converters

Figure 7.

Comparison plots of SHVGC$_{1}$. (a) Parasitic output voltage versus efficiency. (b) Efficiency versus duty ratio.

Figure 8.

Maximum switch voltage stress comparison.

SECTION V. Controller Design

The state-space modeling technique, widely used in linear control theory, is employed to analyze the typical features exhibited by the SHVGC$_{1}$ during its dynamic behavior. Hence, the proposed converter's state-space model is derived using the state-space averaging method. The general representation of the state model is expressed as follows: \begin{align*} {\begin{cases}\dot{x} (t)=A_{j}x(t)+B_{j}u(t)&\\ y(t)=C_{j}x(t)+E_{j}u(t)&\text{where} \ j=1,2.\end{cases}} \tag{45} \end{align*} In the given context, where “$j$” denotes operational states, “$x(t)$” represents the state vector, input vector “$u(t)$” and “$y(t)$” signifies the output vector. By using the operating states of the SHVGC$_{1}$ the state vector “$x(t)$” represents as $[\begin{matrix}i_{L}&i_{L1}&v_{C}&v_{C1}\end{matrix} ]^{T}$, the input vector “$u(t)$” comprises $[ \begin{matrix}v_{i}\end{matrix} ]$, and “$y(t)$” signifies the output vector $[ \begin{matrix}i_{i}&v_{o}\end{matrix} ]$. Using (45), and $A_{\text{avg}}=A_{1}D+A_{1}(1-D)$, $B_{\text{avg}}=B_{1}D+B_{1}(1-D)$, $C_{\text{avg}}=C_{1}D+C_{1}(1-D)$, and $E_{\text{avg}}=E_{1}D+E_{1}(1-D)$ the average state-space model of the SHVGC$_{1}$ is designed and it is expressed as follows: \begin{align*} {\begin{array}{c}A_{\text{avg}}=\left[ \begin{matrix}0&0&\frac{D-1}{L} &0\\ 0&0&\frac{D}{L_{1}} &\frac{D-1}{L_{1}} \\ \frac{1-D}{C} &\frac{-D}{C} &\frac{-1}{RC} &\frac{-1}{RC} \\ 0&\frac{1-D}{C_{1}} &\frac{-1}{RC_{1}} &\frac{-1}{RC_{1}} \end{matrix} \right], B_{\text{avg}}=\left[ \begin{matrix}\frac{1}{L} \\ 0\\ 0\\ 0\end{matrix} \right] \\ \ C_{\text{avg}}=\left[ \begin{matrix}1&0&0&0\\ 0&0&1&1\end{matrix} \right], \ E_{\text{avg}}=\left[ \begin{matrix}0\\ 0\end{matrix} \right]. \end{array}} \tag{46} \end{align*} The linearization of the nonlinear system is achieved through the construction of a small-signal model. This process involves considering all variables ($i_{L}$, $i_{L1}$, $i_{i}$, $D$, $v_{i}$, $v_{C}$, and $v_{C1}$) with their respective quiescent values ($I_{L}$, $I_{L1}$, $I_{i}$, $D$, $V_{i}$, $V_{C}$, and $V_{C1}$), accompanied by small ac signals ($\hat{i}_{L}$, $\hat{i}_{L1}$, $\hat{d}$, $\hat{v}_{i}$ $\hat{v}_{C}$, and $\hat{v}_{C1}$). Therefore, $i_{L}=I_{L}+\hat{i}_{L}$, $i_{L1}=I_{L1}+\hat{i}_{L1}$, $i_{i}=I_{i}+\hat{i}_{i}$, $D=D+\hat{d}$, $v_{i}=V_{i}+\hat{v}_{i}$, $v_{C}=V_{C}+\hat{v}_{C}$, and $v_{C1}=V_{C1}+\hat{v}_{C1}$. Using (46), the small signal model for the converter is obtained and shown in Fig. 9. From the selected values for inductors and capacitors and Fig. 9, we establish the relation between the Laplace-transformed variables $\hat{d}(S)$, $\hat{v}_{i}(S)$, and $\hat{v}_{o}(S)$ as follows: \begin{align*} \hat{v}_{o} (s)=G_{d}(s)\hat{d} (s)+G_{i}(s)\hat{v}_{i} (s) \tag{47} \end{align*} where $G_{d}(s)=\frac{\hat{v}_{o} (s)}{\hat{d} (s)}$ when $\hat{v}_{i} (s)=0$, and $G_{i}(s)=\frac{\hat{v}_{o} (s)}{\hat{v}_{i} (s)}$ when $\hat{d} (s)=0$. \begin{align*} & G_{d}(s)\\ & \!=\! \frac{-1.61 \! \times \! 10^{5}s^{3} \!-\!5.08 \!\times \! 10^{8}s^{2} \!-\! 1.52 \! \times \! 10^{11}s \!+\! 3.25 \! \times \! 10^{14}}{s^{4} \!+\! 23.41s^{3} \!+\! 1.88 \! \times \! 10^{6}s^{2} \!+\! 3.36 \! \times 10^{7}s \! +\! 6.74 \! \times \! 10^{10}} \\ &G_{i}(s)\\ &=\frac{1.35 \! \times \! 10^{6}s^{2} \! + \! 7.68 \! \times \! 10^{-9}s \!+ \!9.18 \!\times \! 10^{11}}{s^{4} \!+ \! 23.41s^{3} \!+ \! 1.88 \! \times \! 10^{6}s^{2} \! + \!3.36 \!\times \! 10^{7}s \!+ \!6.74 \!\times \! 10^{10}}. \tag{48} \end{align*}

Figure 9.

Small signal model of designed SHVGC$_{1}$.

The characteristic equation of the transfer function ($G_{i}(s)$) reveals that all four poles reside on the left-hand side of the s-plane. Consequently, the open-loop system of the designed SHVGC$_{1}$ is stable. The pole locations are $-9.06\pm 191.07i$ and $-2.66\pm 1357.57i$. Given the proximity of the dominant poles to the $j\omega$ -axis, the closed-loop system may exhibit lower relative stability margins. By employing a Bode plot, the frequency response of the transfer function is analyzed. Fig. 10 shows the Bode plot and illustrates that the transfer function without a controller exhibits instability, with a gain margin (GM) of -59.50 dB and a phase margin (PM) of $-91.12^\circ$. A PI controller is designed using the Ziegler–Nichols method, and the parameters are provided as $K_{P}+s^{-1}K_{I}=0.000001+s^{-1}0.0016$ . Fig. 10 also depicts the transfer function with a PI controller. The inclusion of the PI controller transforms the unstable system into a stable one, yielding a GM of 6.69 dB and a PM of $89.84^\circ$.

Figure 10.

Frequency response analysis of designed SHVGC$_{1}$.

SECTION VI. Experimental Validation

The prototype for the SHVGC$_{1}$ design has been fabricated and given Fig. 11 to rigorously assess its performance with specified parameters: an input voltage ($V_{i}$) of 48 V, an output voltage ($V_{o}$) of 650 V, and an output power ($P_{o}$) of 500 W, for the stage of ($n=1$), and the test results are depicted in Fig. 12. In Fig. 12(a), the waveforms for both inductor voltages and currents are presented. Inductor $L$ undergoes charging with an input voltage ($V_{i}$) of 48 V and discharging with a voltage difference of ($V_{i} - V_{C}$), measuring −129 V. Simultaneously, inductor $L_{1}$ is charged with a combined voltage of ($V_{i} + V_{C}$) totaling 177 V, followed by discharging with the voltage ($-V_{C1}$) at a level of -476 V. The results affirm that the inductors' charge and discharge voltage and current waveforms closely align with the analytical equations. Fig. 12(b), the input and output voltage and current waveforms are depicted. The outcomes substantiate that the converter generates a practical output voltage of 649.2 V. Considering the load resistance set at 846 $\Omega$, the practical output power by the converter is 498.4 W. Fig. 12(b), the input voltage is measured at 48 V, and the input current is 10.90 A, resulting in an experimental efficiency of the converter at 96.1%. Fig. 12(c) validates the loop of $V_{i}$-$L$-$D$-$V_{C}$, while Fig. 12(d) illustrates the voltage stress on switches $S$ and $S_{1}$ and the diodes $D$ and $D_{1}$. The voltage magnitudes in these waveforms closely align with the theoretical equations. The maximum voltage stress on switch $S_{1}$ is determined as ${V_{i}D}/{(1-D)^{2}}$, yielding 476 V as depicted in Fig. 12(d). In contrast, the maximum voltage stress on the switch of traditional QBC is ${V_{i}}\,{(1-D)^{2}}$, amounting to 650 V.

Figure 11.

Prototype of proposed SHVGC$_{1}$ converter.

Figure 12.

Hardware results of designed SHVGC$_{1}$. (a) Inductor $L$ voltage ($v_{L}$), Inductor $L$ current ($i_{L}$), Inductor $L_{1}$ voltage ($v_{L1}$), and Inductor $L_{1}$ current ($i_{L1}$). (b) Input voltage ($V_{i}$), Input Current ($i_{i}$), Output voltage ($V_{o}$), and Output current ($i_{o}$). (c) Inductor $L$ voltage ($v_{L}$), Inductor $L$ current ($i_{L}$), Input voltage ($V_{i}$), and Capacitor $C$ voltage ($v_{C}$). (d) Switch $S$ voltage stress ($v_{S}$), Switch $S_{1}$ voltage stress ($v_{S1}$), Diode $D$ voltage stress ($v_{D}$), and Diode $D_{1}$ voltage stress $v_{D1}$.

The SHVGC$_{1}$’s dynamic response is validated by changing the input voltage and load current, and the results are shown in Fig. 13. The output voltage is sensed through the voltage sensor and the corresponding signal is fed to launchpad F28379D. The F28379D microcontroller is compared with the sensed signal with the reference signal through the MATLAB platform, where the error signal is generated, which is given to the designed PI controller. The PI controller generates the pulses to the converter. Fig. 13(a) and (b) demonstrate that the output voltage is regulated to 650 V by varying the input voltage between 48 and 58 V. The output voltage waveform exhibits maximum overshoots and undershoots ranging from 30–40 V, equivalent to 5% to 6% of the reference voltage $V_{0_{\text{ref}}}$. Fig. 13(c) and (d) illustrate the regulation of the output voltage to 650 V. This regulation is achieved by varying the output current between 3.8 and 3.2 A. The output voltage waveform exhibits maximum overshoots and undershoots in the range of 25–30 V, corresponding to 4% to 5% of the reference voltage $V_{0_{\text{ref}}}$.

Figure 13.

Closed loop results. (a) Input voltage change from 48 to 58 V. (b) Input voltage change from 58 to 48 V. (c) Output current change from 3.8 to 3.2 A. (d) Output current change from 3.2 to 3.8 A.

SECTION VII. Conclusion

The proposed converter architecture reduces switch voltage stress compared to the conventional QBC. The analysis of CCM and DCM for the proposed SHVGC$_{n}$ is presented in depth to gain insights into its steady-state operation. The comparative study between converters focused on the rating of elements, efficiency enhancement, and reduction in switch voltage stress SHVGC$_{1}$ is analyzed. The results showed that the proposed SHVGC$_{1}$ performs better than the conventional QBC. The proposed SHVGC$_{1}$ total number of components remains consistent with the conventional QBC, and both configurations exhibit ideally equivalent voltage gains. The reduction in voltage stress in the proposed SHVGC$_{1}$ contributes to a decrease in switching losses, ultimately enhancing its overall performance. The proposed SHVGC$_{1}$ is more efficient and has less voltage stress on the switches. As the number of stages increases, the voltage gain increases, leading to a simultaneous reduction in switch voltage stress. The dynamic behavior of the SHVGC$_{1}$ is analyzed by developing a state-space model using the average small signal technique. The necessary transfer function was derived, and a PI controller was implemented to enhance dynamic performance. Subsequently, all components were designed while considering the worst scenario, and the performance of the designed SHVGC$_{1}$ prototype was validated experimentally for steady-state and dynamic operations.

ACKNOWLEDGMENT

The authors acknowledge the technical support received from the Renewable Energy Lab, and Article Processing Charges (APC) are covered by Prince Sultan University, Riyadh, Saudi Arabia for this publication.