An Ultra Low Steady-State Current Power-on-Reset Circuit in 65nm CMOS Technology

A novel Power-on-reset (POR) circuit is proposed with ultra-low steady-state current consumption. A band-gap voltage comparator is used to generate a stable pull-up voltage. To eliminate the large current consumptions of the analog part, a power switch is adopted to cut the supply of band-gap voltage comparator, which gained ultra-low current consumption in steady-state after the POR rest process completed. The state of POR circuit is maintained through a state latch circuit. The whole circuit was designed and implemented in 65nm CMOS technology with an active area of 120μm*160μm. Experimental results show that it has a steady pull-up voltage of 0.69V and a brown-out voltage of 0.49V under a 1.2V supply voltage rising from 0V, plus its steady-state current is only 9nA. The proposed circuit is suitable to be integrated in system on chip to provide a reliable POR signal.

SECTION I. Introduction

Low power has been a big issue for System on chip (SoC) design, especially for the Wireless sensor networks (WSN) chips and battery supplied mobile applications, where static power is very important ^[1]–​[4]. The static power of SoC is composed of: ① the leakage power of digital circuits which can be cut off by power gating technology, and ② the static power of analog circuits such as Power-on-reset (POR), which is an important part of the static current consumption for most of SoC chips. A POR circuit provides a reset signal to the system during power up stage to ensure the chip can start with aknown state. In many applications, brown-out detection is also needed to reset the system when the supply drops sud-denly in order to protect the system, especially for those with CPUs. What's more, since it is connected to supply voltage all the time, its power consumption is an import part in the chip's whole static power.

Many POR circuits were proposed with different features for different applications ^[5]–​[8], such as near zero steady state current POR^[5], band-gap reference based POR^[6], a long reset-time POR^[7], process and temperature-tolerant POR^[8] and so on. There are also commercial POR Intellectual property (IP) cores provided by IP vendors^[9]. A compact-structured POR is obtained by simply using series connection of an off-chip capacitor and a resistor, with the split voltage connected to several inverters as a buffer to generate the reset signal for the chip^[5]. When the supply voltage V_DD begins to rise from zero, the capacitor begins to charge the input node of the inverter. The reset signal is activated until the voltage of ca-pacitor's upper plate reaches the switching threshold voltage of the inverter with the charging of the capacitor. Although this method is very simplified in its structure, it is not widely used in many applications because ① its pull-up voltage is unstable; ② it can't provide brown-out detection.

The POR circuits based on accurate voltage detection ^[6]–​[8] can obtain a stable pull-up voltage, but at the price of non-negligible static current. A near zero steady-state POR in Ref. [5] provided an on-chip POR reset signal and a brown-out reset signal with near-zero steady-state current consumption. However, it used the split voltage of two resistors in series connection to detect the rise of the supply voltage; therefore, its pull-up voltage is susceptible to the impact of supply voltage and process variations.

Therefore, in this paper, a novel POR circuit composed of a band-gap voltage comparator, a state latch and a brown-out detector is presented, which provides both ultra-low power consumption and stable pull-up voltage. The circuit is designed and implemented in 65nm CMOS technology. The experimental and post simulation results show that it functions well with only several nano-Amp current in steady-state, which is ultra-low.

SECTION II. Circuit Structure and Operating Principle

A novel ultra-low steady-state current POR circuit is proposed as shown in Fig. 1, which is mainly composed of several parts: band-gap voltage detector, current comparator, state latch, brown-out detector and buffer.

To make the pull-up voltage stable, a band-gap voltage detector is employed using band-gap reference and current comparator. And the reset states are stored by state latch circuit. Meanwhile, a power switch transistor is used to cut off the power of the analog parts after the reset process is completed with a stable high output voltage. Therefore, the steady-state current of POR circuit is the leakage current of the digital part, which is of only several nano-Amp.

Fig. 1.

General structure of POR circuit

The whole schematic diagram of our proposed POR circuit is shown in Fig. 2. Their principles are analyzed in the following sections.

1. Band-Gap Voltage Detector Circuit

The band-gap reference circuit shown in Fig. 2 Part $A$ is mainly composed of two pairs of current mirrors by NPN tran-sistors of $Q_{0}, Q_{1}, Q_{2}, Q_{3}$ and two resistors of $R_{1}, R_{2}$. The emitter area of $Q_{1}$ and $Q_{2}$ is set as eight times large as $Q_{0}$ and $Q_{3}{}^{\prime}\mathrm{s}$.

At first when $V_{DD}$ rises from $0, I_{2}$ is larger than $I_{1}$ because the PN junction is cut off until $V_{BE0}=V_{R1}+V_{BE1}$. That is, $I_{2}$ is higher than $I_{1}$ when $V_{DD}$ is lower than the pull-up voltage $V_{TP}$, and it is lower than $I_{1}$ when $V_{DD} > V_{TP}$, then the reset signal generates.

The supply voltage of the band-gap voltage detector is denoted as $V_{E}$, which can be differently described for each branch of $Q_{0}$ and $Q_{1}$ as Eqs.(l) and (2): \begin{gather*} V_{E}=(I_{1}+I_{2}) R_{2}+V_{B E 0}=(I_{1}+I_{2}) R_{2}+V_{T} \ln \frac{I_{1}}{I_{S}}\tag{1}\\ V_{E}=(I_{1}+I_{2}) R_{2}+I_{2} R_{1}+V_{B E 1} \\ =(I_{1}+I_{2}) R_{2}+I_{2} R_{1}+V_{T} \ln \frac{I_{2}}{N I_{S}}\tag{2}\end{gather*}

It can be easily deduced from the equations above that: \begin{equation*} I_{2}=\frac{V_{T}}{R_{1}}\ln\frac{NI_{1}}{I_{2}}\tag{3}\end{equation*}

When $V_{E}$ is equal to the pull-up voltage $V_{TP}$, at this time, $I_{1}=I_{2}=I$, Eq. (3) becomes Eq. (4): \begin{equation*} I=\frac{V_{T}}{R_{1}}\ln N\tag{4}\end{equation*}

The reverse saturation current of PN junction $I_{S}= C_{0}T^{\alpha}\exp(-\frac{V_{g}}{V_{T}})$ ‘ where $C_{0}$ is the diffusion coefficient, $\alpha$ is a constant, $V_{g}$ is the band-gap voltage. Therefore, the pull-up voltage $V_{TP}$ can be modified as: \begin{equation*} V_{T P}=V_{T} \frac{2 R_{2}}{R_{1}} \ln N+V_{T} \ln \frac{V_{T} \ln N}{R_{1}}-V_{T} \ln (C_{0} T^{\alpha})+V_{g}\tag{5}\end{equation*}

The first derivative of $V_{TP}$ with respect to $T$ is: \begin{align*}\frac{d V_{T P}}{d T}= & \frac{2 R_{2} \ln N}{R_{1}} \frac{d V_{T}}{d T}+\frac{d V_{T}}{d T} \ln \frac{V_{T} \ln N}{R_{1}}+\frac{d V_{T}}{d T} \\ & -\frac{d V_{T}}{d T} \ln (C_{0} T^{\alpha})-\frac{\alpha V_{T}}{T}\tag{6}\end{align*}

When temperature is 300K, we can obtain that $dV_{T}/dT= k/q$. It can be deduced that by letting Eq.(6) equal to 0, the pull-up voltage of the POR will be influenced least by the temperature fluctuates near 300K. This is accomplished by designing $R_{1}$ and $R_{2}$ properly according to Eq.(7) to make $V_{TP}$ stable. \begin{equation*}\frac{k \ln N}{q C_{0} R_{1} T^{\alpha-1}}=e^{\alpha-1-\frac{2 R_{2} \ln N}{R_{1}}}\tag{7}\end{equation*}

Then a current comparator circuit is used to compare $I_{1}$ and $I_{2}$ to generate the detection output signal “Det _out” when $V_{DD}$ reaches the pull-up voltage. The currents of NPN tran-sistors $Q_{4}$ and $Q_{5}$ are mirrored from $Q_{0}$ to be compared with the current mirrored from $Q_{1}$. At the beginning of the power-on process, $V_{DD}$ is lower than $V_{TP}$ and $I_{2}$ is higher than $I_{1},M_{5}$ starts to turn on as node $a$ been charged. Meanwhile, the potential of node $b$ keeps low because of that $M_{6}$ is still cut off, $V_{\text {Det}_{-}\text {out}}$ stays low consequently. When $V_{DD}$ rises to the point of $V_{TP}, I_{2}$ is equal to $I_{1}$. After that, $I_{2}$ is lower than $I_{1}$ and node awill be gradually pulled down as $V_{DD}$ exceeds $V_{TP}$, then Det_out will be pulled up as $M_{5}$ turns off and $M_{6}$ turns on.

2. State Latch Circuit

State latch circuit is used here to generate a detection enable signal of “Det_en” to control the power switch of the ana-log part as shown in Fig. 2 Part $A$, which will turn off its power supply after reset process finished. The band-gap voltage de-tector and the state latch are connected through a PMOS tran-sistor $M_{13}$.

It has two working status: first, in the initial stage of power-on, as the supply voltage $V_{DD}$ rises, the voltage at node $n_{1}$ will rise accordingly, and then $n_{2}$ is pulled down that makes $M_{13}$ conductive to latch Det._out is latched as the global re-set signal. Next, when $V_{DD}$ exceeds the pull-up voltage $V_{TP},V_{\text {Det}_{-}\text {out}}$ ramps up and increases as $V_{DD}$ increases. Therefore, as $M_{13}$ is still on, $V_{\text {Det}_{-}\text {out}}$ passes through $M_{13}$ gate to make node $n_{1}$ turn to low voltage, which in turn makes node $n_{2}$ high voltage to turn off $M_{13}$ to isolate analog parts from state latch circuit. Meanwhile, the analog part will be powered off as the power switch transistor $M_{0}$ in Fig. 2 is cut off by the signal buffered from Latch_out.

3. Brown-Out Detector Circuit

A brown-out detector circuit shown in Fig. 2 Part C^[5] is used to generate a reset signal when $V_{DD}$ drops suddenly or when it is too low, in order to prevent the system to work in an unknown state.

When $V_{DD}$ drops suddenly, node $n_{4}$ will stay at a high voltage of $V_{DD}-V_{th}$ just as power supply is still on due to the existence of capacitance $C_{2}$. Afterwards, Latch_out signal and node $n_{3}$ will be pulled down by the output of the inverter composed of $M_{9}$ and $M_{10}$, therefore, the system resets again and power switch $M_{0}$ turns on again for another reset process. It can be seen that when $V_{DD}$ has been stable at high level, the brown-out circuit has little power consumption because there is no direct access from $V_{DD}$ to GND.

Fig. 2.

Schematic diagram of the POR circuit. Part A is the bandgap voltage detector and current comparator; Part B is the state latch circuit, and Part C is the brown-out detector.

SECTION III. Experimental Results

The proposed POR circuit was designed and fabri-cated in SMIC 65nm CMOS technology with an area of 120μm*160μm. Its layout is shown in Fig. 3(a), where most of the areas are occupied by current mirrors of NPN transistors, resistors and capacitance arrays. During the circuit and lay-out design, strict matching and isolation techniques are used to eliminate the influence of process variation. And post simulations are performed to guarantee the correctness of the circuit under different process corners.

Its testing PCB board and the test platform are shown in Fig. 3(b). To be clear, there are only one input and one output in POR: $V_{DD}$ and Por_reset signals. However, it was fabricated together with several other circuits in one chip. Plus, the PCB board was not designed only for our POR circuit. The measure-ment was realized by an oscilloscope, an arbitrary waveform generator, and a digital multimeter.

Fig. 3.

Microphoto of POR circuit and test platform

The experimental results including initial power-on reset, brown-out reset and second power-on reset are shown in Fig. 4, where the power supply is a triangular voltage of 0V to 1.2V. It can be seen that the circuit generates a POR signal when the $V_{DD}$ raises to 0.69V and a brown-out reset signal when $V_{DD}$ drops to 0.49V. When the power supply $V_{DD}$ rises again, the circuit can also generate the correct reset signal. The steady-state current of the POR circuit after the reset prcess finished is ultra low to be measured during the actual chip test by Angi-lent digital multimeter. In order to show how small the steady-state curret is, the post-layout simulation under HSPICE was performed, which showed that except for a pulse current of several micro amps level at the instant of pull-up voltage, the steady-state current of the circuit is only 9nA.

Fig. 4.

Experimental results of initial power-on-reset, brown-out and second power-on-reset

The performance summaries of the proposed POR circuit are listed in Table 1 with comparison to other POR circuits, which shows that our proposed circuit can achieve both stable power-on and brown-out reset with ultra-low steady state current. Here Ref. [5] used the basic structure of series connection of a capacitor and a resistor, which offers medium pull-up voltage stability. Ref.[9] had a low pull-up stability whose V_TP is between l.0V and 1.6V. Although Refs. [7]–​[9] used different CMOS process of 0.18μm, due to the analog pull-up voltage detection circuit, their steady-state current consumptions were among micro-Amps, which should be much larger than the dig-ital leakage current of our work even using the same CMOS process as ours.

Table 1. Performance summaries of the proposed POR circuit and comparisons

SECTION IV. Conclusion

In this paper, a novel power-on reset circuit with both ultra-low steady-state current and a stable pull-up voltage is proposed in 65nm CMOS technology. The POR circuit can perform both power-on reset and brown-out detection. The advantage of our proposed circuit is that it uses a band-gap comparator to generate a stable pull-up voltage. Plus, by using a power gate and a state latch circuit to cut the power supply of the comparator and keep the POR state, the steady state current is ultra-low. Therefore, by reducing the power consumption of the circuit and increasing its stability at the same time, our proposed circuit is suitable to be integrated in large VLSI circuit for low power applications.