A 65nm 687.5-TOPS/W Drive Strength-based SRAM Compute-In-Memory Macro with Adaptive Dynamic Range for Edge AI applications

Analog compute-in-memory (ACIM) has been intensively investigated, pursuing better energy efficiency, network accuracy, and compatibility with various AI models [1–5]. In particular, SRAM-based ACIM macros achieve the flexibility of input/weight (IN/W) allocation incorporating bit-serial inputs, bitwise weight loading across multiple bitlines (BL), and digital shift-and-add multiplication of partial sum ($\mathrm{P}_{\text {sum }}$) in the output line (OL). However, shift-and-add multiplication inevitably exacerbates the $\mathrm{Psum}_{\text {sum }}$ errors arising from the computing/readout process under device mismatches and a limited sensing margin (SM) in ACIM (Fig. 1). This leads to severely erroneous MAC outputs and substantial accuracy loss, impeding the practical utilization of ACIM. To mitigate the Psum errors, the ACIM macro with high-precision IN/W and truncation at the MAC output was proposed [4]. The truncation filters out the quantization noise to an extent, thereby attaining the mitigated accuracy loss. Nevertheless, prior work still suffers from $\mathrm{P}_{\text {sum }}$ errors due to limited $V_{\text {LSB }}$ of high-resolution ADCs. Furthermore, the truncated MAC outputs undermine the advantages of high-precision IN/W undergoing frequent weight updates in ACIM macros. An alternative approach is using a low-resolution ADC with quantization for $\mathrm{P}_{\text {sum }}$ to secure higher $\mathrm{V}_{\text {LSB }}$ and suppress the resultant $\mathrm{P}_{\text {sum }}$ error [5]. However, under high macro utilization, it eventually suffers from accuracy loss due to quantization error, which is amplified by the shift and adder. To address the challenges, the drive strength-based SRAM compute-in-memory (DS-CIM) macro is proposed featuring: 1) $6 b$ drive strength-mode sensing with adaptive dynamic range that secures up to $39.2 x$-boosted sensing margin and 97% of error-free Psum readout on 2’s-complement 4b-IN/W ResNet-20 benchmarks, 2) row-wise adaptive dynamic range SAR (ADR-SAR) logic enabling concurrent ADC readout at every OL with the area efficiency of 15.83 TOPS $/ \mathrm{mm}^{2}, 3$) input-aware binary search (IABS) reducing average ADC conversion cycles by 64% on the ResNet-20 benchmark, and 4) a heterogeneous logic unit (HLU) for column-wise logic reconfigurability.