Contents I. Introduction
As more and more integrated circuit (IC) designs are sourced externally, concerns about design reliability and security have increased. Third-party foundries could potentially steal intellectual property (IP) [1], counterfeit or overproduce ICs [2], [3], or insert layout Trojans [4], [5], [6]. These hardware attack modalities have targeted both digital and analog IPs. Large semiconductor companies, primarily focused on digital computing infrastructure, dominated the industry over last decades. Consequently, research has predominantly centered on techniques to protect digital IPs, including encryption [7] and logic-locking [8], [9], [10]. However, analog hardware is expected to dominate the future growth of semiconductors due to its application in future technologies such as artificial intelligence (AI), autonomous driving, 6G, and the Internet-of-Things (IoT) [11]. However, only limited research exist for locking analog IPs [12], [13], [14], [15]. Analog circuits are also easily identifiable in layout due to unique characteristics such as variety of components and sizes, symmetry in design, use of dummy devices, guard rings, well proximity and matching, and custom layout for performance optimization. There is a need to develop comprehensive analog IP locking techniques. This necessity arises not only due to the projected growth of analog hardware but also because analog circuits consistently undertake critical tasks, even within predominantly digital ICs.
