Constraint Symbolization Method for Analog Layout Retargeting with Geometric Programming

To satisfy the requirements of complex and special analog layout constraints, a constraint symbolization method based on geometric programming for analog layout retargeting is presented in this paper. Our approach is to build symbolic template for layouts, then uses Geometric programming (GP) to achieve new technology design rules, implement device symmetry and matching constraints, and manage parasitics optimization. The GP, a class of nonlinear optimization problem, can be transferred or fitted into a convex optimization problem. Therefore, a global optimum solution can be achieved. The symbolization method ensures the layout retargeting automatically. The efficiency and effectiveness of the proposed algorithm, as compared with the other existing methods, are demonstrated by a basic case-study example and a two-stage Miller-compensated operational amplifier.

SECTION I. Introduction

The demands for mixed-signal integrated circuits are growing for applications in telecommunication, consumer products, computing and automotive sectors. Multiple functionalities such as digital, analog, and even radio frequency, which used to reside on many different chips, are now converging into one or a few chips. Even though analog part normally occupies a small fraction of the entire silicon area in a mixed-signal chip, analog circuit design has been recognized as a bottleneck due to its low productivity and high sensitivity to complex constraints.

Recently, significant progress has been made in the ana-log circuit optimization tools, which automatically synthesize circuit topologies, device sizes, and biasing to meet desired specifications. However, the performance of the analog ICs is strongly dependent on layout geometry and style. Several factors, such as device symmetry, matching, and interconnect par-asitics, are of immense importance in ensuring desired circuit performance^[1]. The complexity associated with adequately modeling these effects poses great challenges to analog layout automation.

Over the years, several CAD tools have been developed to automate the generation of analog layouts. However, as some of these tools (such as Ref. [2]) are developed for the system designers, the circuit designers tend to experience difficulties in integrating their design knowledge and experience into the design flow. Even though this problem has been addressed in KOAN/ ANAGRAM II and LAYLA^[3], the construction of an entire analog layout in these systems is based on non-optimal single devices rather than decomposed subcircuits, which in-evitably increases the computation complexity, especially for larger circuits.

Driven by the need for high speed, low voltage, and low power, semiconductor manufacturers continue to develop tech-nologies towards even smaller transistor feature sizes. To convert a carefully handcrafted layout in an old technology to a new process, Computer-aided design (CAD) tools can speed up the design procedure. For the digital portion of the mixed-signal systems, the layout retargeting can be easily achieved using modern cell-based tools. However, analog designers do not have comparable facilities, and thus have to work on a time-consuming full cycle of redesign, layout, and testing. To get new products to market fast and painlessly, analog layout retargeting has become an attractive research topic in both academia and industry.

Jangkrajarng et al. developed a CAD tool called IPRAIL^[4] to retarget an existing analog layout to new processes. Starting from an already fine-tuned input layout, IPRAIL first extracts a structural template, and then automatically generates the final layout by imposing new device sizes and new design rules on the template. Linear Program-ming is used to achieve retargeting with the consideration of design rules and symmetry constraints. However, layout par-asitics, which have significant impact on circuit performance, are not regarded. To address this problem, others proposed a nonlinear programming solution to solve parasitic-aware ana-log layout retargeting. Due to the nature of nonlinear programming, although powerful, may not find a global solution even when it does exist. In particular, any nonlinear programming solver is not able to guarantee to always find the global optimum when searching for the solution. In this paper, we are motivated to reformulate the problem so that the parasitic-aware retargeting can be solved in a systematic manner. A constrains symbolization process based on geometric programming has been presented to retarget analog layout. The Geometric programming (GP)^[5] guarantee the global op-timum, as standard form of GP ensures that GP can be readily turned into a convex optimization problem, whose tractability is roughly equal to linear programming ^[6]. The constraint symbolization method ensures the analog layout automatic re-targeting.

The rest of the paper is organized as follows. Section II illustrates Geometric programming for analog layout retargeting. Section III details the features of Constraint symbolization method and procedure. Section IV reports the experimental results based on several case studies and compares these results with those obtained using IPOPT. Finally, the conclusion is drawn in Section V.

SECTION II. Geometric Programming

The Geometric programming (GP) is a type of mathematical optimization methods characterized by objective and constraint functions that have a special form. The GP can be converted or fitted into a convex optimization problem. Thus, a global optimum solution can be achieved based on GP; in particular, the final solution is completely independent of the starting point. Recently developed methods can solve even extremely large-scale GPs efficiently and reliably. A number of practical problems, particularly those found in circuit design, have been found to be equivalent to (or well approximated by) GPs. The basic approach in GP modeling is to attempt to express a practical problem, such as power control or transistor sizing, in the GP format. If we succeed in formulating a practical problem as a GP, the problem can be effectively and reliably solved by a well developed GP solver package.

1. Monomial and Posynomial Functions

Let $x_{1}, \cdots, x_{n}$ denote $n$ real positive variables, and $x = (x_{1}, \cdots, x_{n})$ is a vector with components $x_{i}$. A real valued function $f$ of $x$, with the form:

$$\begin{equation*} f(x)=cx_{1}^{a_{1}}x_{2}^{a_{3}}\cdots x_{n}^{a_{n}}\tag{1}\end{equation*}$$ where $c > 0$ and $a_{i}\in R$, is called a monomial function. We refer to the constant $c$ as the coefficient of the monomial and the constants $a_{1}, \cdots,a_{n}$ as the exponents of the monomial. Therefore, the monomial will refer to the definition given above, in which the coefficient can be any positive number and the ex-ponents can be any real numbers. A posynomial function is a sum of one or more monomials in the form: $$\begin{equation*} f(x)=\sum_{k=1}^{K}c_{k}x_{1}^{a_{1k}}x_{2}^{a_{3k}}\cdots x_{n}^{a_{nk}}\tag{2}\end{equation*}$$ where $c_{k} > 0$, is called a posynomial function. The posynomial is meant to the sum of many positive polynomials.

2. GP Standard Forms

A geometric program is an optimization problem of the form Ref. [5]

$$\begin{align*}\text{minimize} &\quad f_{0}(x) \\ \text { subjectto } &\quad f_{i}(x) \leq 1, \quad i=1, \cdots, m \\ &\quad g_{j}(x)=1, \quad j=1, \cdots, p\tag{3}\end{align*}$$ where $f_{i}$ is a posynomial function, $g_{i}$ is a monomial, and $x$ is the vector of optimization variables. The problem Eq.(3) is the standard form of the geometric programming. In this form, the objective function must be posynomial and minimized. The equality constraints can only be a monomial equal to one, whereas the inequality constraints can only be a posyn-omialless than and equal to one. The aim of forming monomial and posynomial in the objective and constraint functions is to build up a problem that can be easily converted to and solved by convex optimization. After a real problem has been mod-eled in the form of GP, the global optimum can be achieved by invoking a well-developed GP solver package.

SECTION III. Constraint Symbolization Method and Procedure

1. Layout Retargeting

Layout retargeting refers to generation of a target layout from an existing one. This process is especially useful when making an old design migrate to new technologies or updated specifications. The goal of the retargeting is to generate a new layout with minimum area while satisfying the required constraints.

To retarget the old design to a new layout, a set of constraints corresponding to technology design rules, layout symmetry, geometry proximity, especially parasitics are first extracted from the existing layout. These constraints force the target layout to retain floorplan, symmetry and other proper-ties of the existing layout while still meeting the new technology design rules and the updated design specifications. More-over, to ensure desired circuit performance, the values of par-asitic resistances and capacitances must be controlled when retargeting. Parasitic-aware layout retargeting can be solved as a general compaction problem plus additional geometric constraints due to parasitic. The Constraint symbolization method to build constraint used in GP are formulated in Fig. 1.

Fig. 1.

Constraint symbolization method

During the constraint symbolization method, the constraints in horizontal direction for transistors are symbolized as variables $x_{i}$, also the we can set $y_{i}$ for vertical direction. These variables $x_{i}$ and $y_{i}$ are used to build constraints in GP with representing the relative relationship between each oth-ers.

2. Design Flow

After the constraint symbolization method used, we can achieve a symbolic template for the old layouts. The design flow for whole layout retargeting from old design to a new one can be described in Fig. 2.

Fig. 2.

Analog layout retargeting design flow

We first extract expertise embedded in an existing layout to construct a symbolic template composed of a set of linear constraints. With the circuit netlist extracted from the layout, a sensitivity computation engine conducts simulations to automatically generate a set of performance sensitivities. Nonlinear sensitivity-based performance constraints are then incorporated into the template, given the target technology, new device sizes, symmetry, etc. Finally, a target layout is generated by solving the formed compaction problem with a geometric programming solver.

SECTION IV. Experimental Analysis

In this section, a basic case study example is first given to demonstrate the Constraint symbolization method and work flow for analog layout retargeting as discussed in the paper. Then a two-stage Miller-compensated operational amplifier is analyzed to demonstrate the performance of the GP method in the analog layout retargeting.

1. The Basic Case Study

Layout optimization and retargeting refer to generation of a new target layout from an existing one. This is especially useful when migrating technologies or changing design specifications. A set of constraints corresponding to technology design rules, layout symmetry, geometry proximity, etc. are first extracted from the existing layout. These constraints force the target layout to retain floorplan, symmetry and other proper-ties of the existing layout while still meeting the new technology design rules and the updated design specifications. The objective of optimization and retargeting is to generate the target layout with the minimum area satisfying the imposed performance specifications.

The layout structure of the basic case is shown in Fig. 3. In the example, the related constraints include not only the design rules, but also device symmetry constraints as well as the requirements of parasitic resistance and capacitance. Two MOSFETs are connected at the gate terminals and they are symmetric with respect to $x_{21}$ line. To apply the GP modeling, we build the coordinate system and label it with $x$ (for horizontal dimension) or $y$ (for vertical dimension) followed by a number. The steps for GP modeling are presented below.

Fig. 3.

Layout for geometric programming application

(1) New Design Rules and Symmetry Implementation

Based on the new process, the design rules and device symmetry constraints can be represented in the equations and inequalities with constraint symbolization method shown in Eq.(4):

$$\begin{align*} & x_{i}-x_{j} \geq 0, \quad y_{i}-y_{j} \geq 0 \\ & x_{i}-x_{j}=0, \quad y_{i}-y_{j}=0 \\ & x_{i}-x_{j} \geq A, \quad y_{i}-y_{j} \geq B \\ & x_{i}-x_{j}=C, \quad y_{i}-y_{j}=D \\ & x_{i}-x_{i-1}=x_{i+1}-x_{i} \\ & (i=1, \cdots, 20, \quad j=1, \cdots, 20)\tag{4}\end{align*}$$ where $A, B, C$, and $D$ are positive numbers and are determined by technology design rules. For example, a minimum extension design rule can be represented by $x_{1}-x_{17}\geq 4$ and device symmetry constraint can be imposed by $x_{21}-x_{18}=x_{19}-x_{21}$. For $x_{1}-x_{17}\geq 4$, it can be converted into $4\times x_{1}^{-1}+x_{17}\times x_{1}^{-1}\leq 1$. As for $x_{21}-x_{18} = x_{19} - x_{21}$, it can be converted into 0.5 $\times x_{18}x_{21}^{-1}+0.5\times x_{19}x_{21}^{-1}=1$.

(2) Parasitics Optimization

Device floorplan, symmetry, proximity, and interconnect parasitics are significant factors in ensuring desired circuit performance. Layout parasitics can arise from transistor source and drain capacitances, resistances and capacitances in inter-connections, and coupling capacitances between interconnect wires. These parasitics significantly affect circuit performance such as gain, bandwidth, phase margin, etc. Thus, parasitic issues must be clearly addressed in a successful analog design.

To ensure desired circuit performance, two criteria are required for all interconnect parasitics. First, for sensitive nets in the design, resistance and capacitance need to be restricted within certain bounds. Second, the parasitics of some nets must be closely matched to those of other nets. This is required in some symmetric structures, such as differential pairs. When retargeting an analog layout from an available technology process to a new one, the parasitics influence must be analyzed for optimal solution. For the example in Fig. 2, the interconnect parasitics can be calculated by Eq.(5).

$$\begin{align*} R & =\rho_{s h} \times(length / width) \\ C_{s u b} & =c_{a} \times(length \times width)+c_{s w}(2 \times length) \\ C_{coup } & =c_{c} \times(length / distance)\tag{5}\end{align*}$$ where $\rho_{sh}$ is sheet resistance per unit square, $c_{a}$ is substrate capacitance per unit area, $c_{su}$ is sidewall substrate capacitance per unit length, and $c_{c}$ is coupling capacitance per unit length. For example, resistance parasitic in Fig. 2 can be represented by $$\begin{equation*} R_{contact }=0.078 \times\left(\frac{y_{3}-y_{1}}{x_{10}-x_{9}}+\frac{x_{11}-x_{10}}{y_{2}-y_{1}}+\frac{y_{4}-y_{1}}{x_{12}-x_{11}}\right)\tag{6}\end{equation*}$$

For $R_{contact}$, when using $t_{i}$ as upper bounds, it can be transformed into Eq.(7) which satisfies the requirements of a GP standard form. During the transformation, we have used the inequality $1/(a+b)\leq 1/a+1/b$, where $a$ and $b$ are positive monominals. The same methods are also effective for capacitance parasitics.

$$\begin{align*} & 0.078 \times(t_{1}+t_{2}+t_{3}) \leq R_{upper bound }\\ & m_{1} \times t_{1}^{-1} \times x_{10}^{-1}+x_{9}^{-1} \times x_{10}^{-1} \leq 1, y_{3} \times m_{1}^{-1}+y_{3} \times y_{1}^{-1} \leq 1 \\ & m_{2} \times t_{2}^{-1} \times y_{2}^{-1}+y_{1}^{-1} \times y_{2}^{-1} \leq 1, x_{11} \times m_{2}^{-1}+x_{11} \times x_{10}^{-1} \leq 1 \\ & m_{3} \times t_{3}^{-1} \times x_{12}^{-1}+x_{11}^{-1} \times x_{12}^{-1} \leq 1, y_{4} \times m_{3}^{-1}+y_{4} \times y_{1}^{-1} \leq 1\tag{7}\end{align*}$$

(3) Results and Analyses

Three packages, IPOPT, Linear programming (LP)^[7] and GP packages ^[8] have been used for the case study. The results are summarized in Table 1.

Table 1. Retargeting results for the case study

In Table 1, the target values in second row are the ideal solution to this case study. The runtimes present the efficiency of the algorithms. The values in the LP row are results from using linear programming package. The values in the IPOPT1 row are achieved when setting variables with a range from -100 to 100. The values in the IPOPT2 row are achieved when setting variables with a shrunk range from 0 to 100. However, for the proposed GP method, we do not need to set range for variables.

From Table 1, we can find that the area results 624 from LP method are greater than the target value 608, although its runtime is only 18. The search capability of the IPOPT scheme is limited by the preset variable ranges, and its capacitance is 0.0005 which are greater than that of GP. The derived area values for IPOPT1 are 608 and 615 for IPOPT2 compared with the target value is 608. The difference results from the limit of IPOPT algorithm. In contrast, the GP method, which achieves 608 for the area objective, can find optimal solution without predefining variable range. And the runtime for the GP method is shorter than that of the IPOPT approaches. Moreover, the resistance and capacitance from the GP is 0.0001Ω and 0.0002pF respectively, compared with 0.0005Ω and 0.0005pF for IPOPT1 and IPOPT2 respectively. The experimental results show that the proposed GP method is more effective than the linear programming and IPOPT approachs for the parasitic-aware layout retargeting.

2. Two-Stage Miller-Compensated Operational Am-Plifier

The second example is to related to a specific circuit when considering the circuit performances. The two-stage miller-compensated operational amplifier is depicted in Fig. 4. The circuit was designed initially in a 0.25μm CMOS process and retargeted to a 0.18μm process with new specifications.

Fig. 4.

Two-stage Miller-compensated opamp

Layout parasitics have significant impact on circuit performances like gain, bandwidth, phase margin, etc. For the example, circuit performances have been simulated based on the layout results obtained from the IPOPT, GP and LP pack-ages after layout retargeting. Five main parameters have been chosen for the analysis. The results are summarized in Table 2.

Table 2. Circuit performance for two-stage Miller-compensated operational amplifier

In Table 2, BW, GM, and PM refer to bandwidth, gain margin, and phase margin, respectively, and area is the retargeted layout area. The specification of gain is 60.0db; however the gain value of LP is only 59.1db. The results of Lin-ear programming (LP) failed to meet the design specifications due to linearization. Although the BW value (104.9 MHz) of GP is less than that of IPOPT (105.1), the GM value (18.7) and PM value (91.0) of GP are greater than those of IPOPT. Moreover, the results of GP and IPOPT both satisfy the circuit performance specifications. As for layout area, the important parameter for the layout retargeting, the result using GP package is 3022μm² which is less than that of LP (3102) and IPOPT (3084). This example further demonstrates that the GP method is an efficient and effective algorithm for the analog layout retargeting.

SECTION V. Conclusion

In this paper, a new analog layout retargeting approach using constraint symbolization method and geometric program-ming was presented and illustrated. The layout retargeting includes specifications of the new design rules, and considers issues significantly impacting on the circuit performance such as device symmetry, matching constraints, and parasitics optimization. The constraint symbolization method ensures the layout retargeting automatically. The geometric programming ensures the optimization results are global solution and the circuit performance can be achieved. The experimental results of the two transistors and the two-stage miller-compensated operational amplifier were obtained using the geometric program-ming. The results demonstrated the efficiency and effectiveness of the proposed method. Note that for the GP method, a global optimal solution can be achieved without having to set variables' ranges or select specific starting points.

The authors would like to thank Dr. lihong Zhang in Canada for very useful ideals and suggestions to start the whole work flow.