Efficient Architectures of FIR Filters using Distributed Arithmetic

This research presents an overview of the Finite impulse response (FIR) filter architectures that utilize distributed arithmetic design (DAD). This paper reviews non-reconfigurable as well as reconfigurable FIR filter architectures using DA. General Multiply Accumulator (MAC) based FIR filter architectures require large chip area, consume more power and enforce a limitation on the order of filters. DAD technique is a bit serial operation which has high throughput processing capability, cost effective, area and power efficient. This paper presents different realizations of FIR filters using different DAD techniques namely LUT based DAD, LUT-Less DAD, shared LUT based DAD. This paper presents a comparative analysis of different DA based FIR filters and can form a basis for further work on DA based reconfigurable FIR filters