Signal Integrity Simulations of 4JL Gate Pulses from 4 K to 50 K

Digital communication between temperature stages is a critical part of superconducting electronics systems. Specifically, enabling clean, low-loss communication between single flux quantum (SFQ) circuits at 4 K and CMOS circuitry and memory at higher temperature stages (such as 50 K) can allow for significantly more system memory than what current superconducting devices and memories allow. An amplifier for SFQ pulses, such as a four-junction logic (4JL) gate, must also be included at the beginning of the data link. We have simulated such a data link in Pathwave ADS, which uses four-junction logic (4JL) gate characteristics that were initially simulated in JoSIM. ANSYS HFSS was used to generate the S-parameters used in ADS. Eye diagrams generated from the ADS simulation results are analyzed. The eye diagrams from the data link give an eye width of 77.2 ps and an eye height of 2.16 mV in the worst case, compared to an eye width of 94.3 ps and an eye height of 4.24 mV from the 4JL gate. These simulations will enable future hardware implementations of SFQ to CMOS memory data links.