Contents I. Introduction
Traditionally, the semiconductor industry relied on monolithic SoC chips where a single die provides all the required functionality. But with increasing compute power and feature demand, die sizes grew to the extent that it became challenging to manufacture them with acceptable yield, because larger dice tend to have more defects. As a result, the industry has adopted a multi-die packaging approach, which is gaining popularity. After composing a multi-die package, testing is often performed to ensure that various dice of the package operate within defined parameters. This testing requires a die to have a direct connection to the package IO. When a package has a large number of dice, it is often not feasible to provide every die a direct IO connection. Many times, such packages are architected in a configuration where one die provides IO access (IO-die), and other dice (core-dice) are connected to the IO-die using a die-to-die interconnect, as shown in Fig. 1. In this configuration, the die-to-die interconnect may become the bottleneck for the test data transfer. If the die-to-die interconnect is functionally a high-speed serial interface with a limited number of lanes, parallel test data transfer through such an interconnect is severely limited, resulting in increased test time and higher production costs. To overcome this limitation, it is desirable to serialize the test data as well. However, such serialization and de-serialization of the test data must be transparent to ATPG tools, providing high bandwidth without impacting the rest of the test environment. Additionally, this method must ensure that the same ATPG patterns are reusable for both wafer sort and final package testing. This paper discusses such a scan SerDes implementation to reduce the production cost of multi-die packages with limited underlying die-to-die link width. It appears simply as a fixed number of pipeline stages to the ATPG tools and provides a large number of virtual scan channels over a limited number of die-to-die interconnect lanes. Furthermore, it introduces minimal programming overhead, with just a few additional TDR configuration writes. Inherent indeterminism related to SerDes links is also addressed, ensuring that scan SerDes operates deterministically under any test corner. Moreover, the entire solution is implemented using synthesizable RTL, without custom circuits, and relies solely on standard cell library components.
