Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques

This article proposes a mm-wave fractional-N ADPLL employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, consequently improving jitter at lower power consumption while using a low-frequency reference of 50 MHz. The passive over-sampling PD utilizes a zero-forcing technique for voltage-domain presetting and compensation for both the fractional phase and reference spurs induced by imperfections in the reference waveform and ROS-PD. The ROS-PD eliminates the conventional power-hungry low-noise buffer for the reference input and reduces the PD noise by increasing the loop correction speed. This promotes low jitter and high efficiency in advanced mm-wave PLLs without relying on the increase of the reference clock frequency to several hundred MHz. The imperfections in the reference waveform and ROS-PD, i.e., harmonic distortion, differential path mismatches, and other non-ideality factors, can be programmably compensated by the proposed digital manifold calibration scheme, resulting in low reference spurs. A class-F3 oscillator is used to generate a 10 GHz signal for the feedback divider along with its 3rd harmonic for the harmonic extractor to generate the 30 GHz output. The proposed ADPLL is implemented in TSMC 28-nm LP CMOS. The prototype generates a 24–31 GHz output carrier with rms jitter of 237 fs while consuming only 12 mW. This corresponds to a state-of-the-art ADPLL FoMjitter-N of –269 dB in a fractional-N mode. Using a comprehensive digital calibration, the reference spurious tones can be reduced from –33 dBc to –65 dBc.