An Energy-Efficient Low-Voltage SRAM-based Charge Recovery Logic Near-Memory-Computing Macro for Edge Computing

In this paper, an energy-efficient low-voltage 7T SRAM-based charge recovery logic NMC macro is proposed. Firstly, a weight-stationary NMC macro architecture in dual clock and voltage domains is proposed to save memory energy consumption at near-threshold regime, without sacrificing computing throughput. Secondly, the charge recovery logic at subthreshold regime is also employed to reduce NMC logic energy consumption, while maintaining the computing speed. Simulation results show that the energy efficiency of the proposed 4Kb 7T -SRAM based CRL NMC macro design is around 3.71 TOPS/W, i.e., $6.49 \times$ improvement against the baseline design, when accelerating convolutional operations by 1.8 GOPS at 100 MHz with SRAM operating under 0.6 V and CRL computing under 0.4 V.