Improved Frequency Response of Two Stage Amplifier using Cascode Current Mirror and Voltage Buffer Circuit | IEEE Conference Publication | IEEE Xplore
Scheduled Maintenance: On Monday, 30 June, IEEE Xplore will undergo scheduled maintenance from 1:00-2:00 PM ET (1800-1900 UTC).
On Tuesday, 1 July, IEEE Xplore will undergo scheduled maintenance from 1:00-5:00 PM ET (1800-2200 UTC).
During these times, there may be intermittent impact on performance. We apologize for any inconvenience.

Improved Frequency Response of Two Stage Amplifier using Cascode Current Mirror and Voltage Buffer Circuit


Abstract:

In an effort to enhance the amplifier's frequency response, this study presents a two-stage design that includes a voltage buffer and cascode current mirror. The proposed...Show More

Abstract:

In an effort to enhance the amplifier's frequency response, this study presents a two-stage design that includes a voltage buffer and cascode current mirror. The proposed design achieves a gain of 75.3 dB, a Gain Bandwidth Product (GBW) of 14.4 MHz, and a phase margin (PM) of 50°. Furthermore, it exhibits a 77.6 dB Common Mode Rejection Ratio (CMRR) and a Power Supply Rejection Ratio (PSRR) of 63.24 dB. Tanner Tool with TSMC 0.18 μm CMOS technology is used to run the simulation.
Date of Conference: 07-09 August 2024
Date Added to IEEE Xplore: 02 October 2024
ISBN Information:

ISSN Information:

Conference Location: Coimbatore, India

Contact IEEE to Subscribe

References

References is not available for this document.