A 12 ps Precision Two-Step Time-to-Digital Converter Consuming 434 μW at 1 MS/s in 180 nm CMOS With a Dual-Slope Time Amplifier

A two-step time-to-digital converter (TDC) is designed for the high-precision time measurement of the DIRC-like TOF (DTOF) detector at the Super Tau-Charm Facility (STCF). Extending the measurement range by Nutt’s method, the TDC clock cycle is interpolated with two voltage-controlled tapped delay lines (TDL) connected by a dual-slope time amplifier (TA). By amplifying the residue from the first-step TDL-based interpolation with the TA and measuring it with the second TDL, the TDC resolution is significantly improved to sub-gate delay. Since the residue is extracted by a new method without the need of TA duplication or delay insertion, the TDC power consumption and conversion time are effectively reduced. By adopting the improved TA circuit into the TDC with a high gain, adjustable output offsets, and good linearity, the TDC measurement precision is guaranteed. In addition, a new DLL structure is proposed to stabilize the TDL against process, voltage, and temperature (PVT) variations with less power consumption. Benefiting from the proposed residue extraction method and DLL structure, the TDC exhibits low power consumption. To verify the TDC design, a prototype chip with two TDC channels is fabricated in GlobalFoundries (GF) 180 nm CMOS technology for performance evaluation. With a system clock of 150 MHz, it has a resolution (LSB) of 16.5 ps and a maximum sample rate of 6 MS/s. The differential nonlinearity (DNL) error ranges from −0.98 LSB to 0.87 LSB and the integral nonlinearity error (INL) ranges from −4.21 LSB to 2.83 LSB. With a bin-by-bin calibration method, the measured TDC precision is 12.1 ps on average within the 0–20 ns time interval measurement range. In addition, the TDC has low temperature sensitivity and does not require recalibration within a 20 ° C temperature range. Each TDC channel consumes $434~\mu $ W power at 1 MS/s sample rate. The test results confirm that the proposed TDC can achieve high precision with a moderate sample rate and low power consumption without highly scaled technologies, which can meet the requirements of the DTOF detector at STCF.

I. Introduction

Time-to-digital converter (TDC) is the core device in time measurement, which is widely used in high-energy physics [1], [2], light detection and ranging (LiDAR) systems [3], [4], medical imaging [5], [6], digital phase-locked loop (DPLL) [7], [8], and analog-to-digital converter (ADC) [9], [10]. At the Super Tau-Charm Facility (STCF) in China, the endcap region particle identification (PID) system detects the internally reflected Cherenkov light (DIRC) and measures its time-of-flight (TOF) to identify charged particles produced by the collision of electrons and positrons. As shown in Fig. 1, TDC in the DIRC-like TOF (DTOF) detector is responsible for the quantization of the time of arrival (TOA) and time-over-threshold (TOT) of the photon signal. For excellent PID capability, the DTOF detector is required to have a single-photon time resolution of better than 50 ps [11], which needs the timing uncertainty of the readout part to be no more than 43 ps. After deducting the contributions from the photosensor (32 ps), amplifier and discriminator (20 ps), and clock synchronization (15 ps), the time measurement precision of TDC should be better than 15 ps. In addition, the TDC has to reach a sample rate of several megahertz, a large measurement dynamic range, and relatively low power consumption to fulfill the operation and integration requirements of STCF. Fig. 1.

Illustration of the DTOF detector at STCF.