Inversion Coefficient as a Key Design Parameter in MOS Device Performance

The paper discusses MOS device performance using the EKV model and its key parameter, the inversion coefficient (IC), for the 90nm CMOS process. The study includes sizing relationships, DC bias parameters, small signal parameters, gain and bandwidth relationships, gate referred thermal and flicker noise parameters, local area DC mismatch parameters, gate-source leakage current and figure of merit factors for low power RF designs. By using charts versus IC, the graphical view illustrates MOS performance tradeoffs. By introducing the MOSFET operating plane, optimal bias points for the best MOS performance can be selected. It is observed that the moderate inversion region is the most suitable for low-power design.