Multi-Domain Dynamics and Ultimate Scalability of CMOS-Compatible FeFETs

Recent research on CMOS-compatible FETs aims at aggressive scaling, targeting advanced performance nodes (7 nm - 14 nm), with the ultimate scalability limit posed by direct source-to-drain tunneling (DSDT). This letter investigates the impact of multi-domain dynamics in the ferroelectric gate dielectric on FeFET scalability. Coupled solutions of 2-D Poisson’s equation with the ferroelectric’s 2-D thermodynamics model (depolarizing energy + gradient energy + free energy) are the basis of a phase-field model. Varying ferroelectric and dielectric layer thicknesses can be used to engineer domain density. Minimal DSDT, maximum ON/OFF current ratio, and maximum memory window (MW) are possible when a single domain wall (domain density = 2) is located near the mid-channel. Additional domain walls increase DSDT. Furthermore, the drain electric field shifts the domain wall towards the source, increasing DSDT. Spatial gradient in polarization drastically impacts DSDT, with hard domain walls exhibiting lower DSDT due to increased polarization gradient. Our study predicts an optimal physical gate length of 12 nm (domain density = 2) with I $_{\textit {ON}}$ /I $_{\textit {OFF}}~\sim ~{1}\times {10} ^{{6}}$ and subthreshold slope $\sim ~100$ mV/dec.

I. Introduction

The utilization of hafnium-based ferroelectric FETs (FeFETs) has emerged as a promising avenue in the development of non-volatile memory, primarily owing to their compatibility with CMOS processes and their scalability [1], [2], [3], [4]. The scalability of hafnium-based ferroelectric FETs (FeFETs) in terms of gate length () has been a focal point in recent research endeavors. Experimental investigations have showcased significant progress in this area, with reported values of 10 nm [5], 20 nm [6], and 30 nm [7]. Complementary to these experimental findings, phase-field and TCAD simulations have further elucidated the gate length scalability, proposing values of 30 nm [8], 22 nm [9], and 24 nm [10]. It is evident that in Si channel-based FETs ( nm), the scaling limit is predominantly imposed by the direct source to drain tunneling (DSDT) [11].