A Complementary Resistive Switch-Based Balanced Ternary Logic

Memristors offer advantages in terms of high speed, high integration density, and non-volatility, making them a promising option for efficient logic applications. Recent works have explored the design methodology for ternary logic in memristor-based computing-in-memory (CIM) systems. However, existing methods require a large number of devices and are susceptible to noise interference. To address these issues, this work proposes a reliable in-memory computing paradigm for balanced ternary logic based on complementary resistive switch (CRS), which can be considered as two anti-serially connected memristors. Six balanced ternary logic gates are designed based on the proposed method, which support parallel operations when integrated into the CRS crossbar array. To demonstrate the efficiency of the proposed method, a 1-tri full adder is designed by using the proposed logic gates. The feasibility of the design is verified by Cadence Virtuoso using the Voltage Threshold Adaptive Memristor (VTEAM) model. The Monte Carlo simulation of the full adder verifies the reliability of the proposed method. Compared to existing methods, both the operation steps and area overhead are reduced using the proposed approach.