Measurement and Analysis of On-Wafer Test Structures for Signal Integrity Assessment at Chip Level

This paper presents the characterization and analysis of thin film microstrip line coupled test structures designed for evaluating Signal Integrity (SI) and Power Integrity (PI) up to 50 GHz on chips such as Field Programmable Gate Arrays. Several test structures were designed and fabricated on SU-8 photoresist thin film. SI and PI related performance parameters such as mismatch, distortion, crosstalk, and power distribution network voltage drops are emphasized by varying the dimensional characteristics of the test structures, such as the line width, length, bending and presence of neighbor traces. Additionally, calibration standards utilizing the multimode TRL calibration technique were implemented on the same chip to allow the test structures to be characterized by measuring their mixed-mode S parameters.