3-D Self-Aligned Stacked Ge Nanowires Complementary FET Featuring Single Gate Simple Process

In this study, we experimentally demonstrated a state-of-the-art three-dimensional (3-D) self-aligned stacked hetero-oriented p-type Ge rectangle nanowire (NW) gate-all-around field-effect transistor (GAAFET) on n-type Ge diamond NW GAAFET of single-gate complementary FET (CFET). Anisotropic and isotropic dry etching processes are used to form the stacked NWs. Using Ge as the channel material with its optimal surface orientations of (111) for diamond NW nFET and (110) for rectangle NW pFET can enhance the device performance. The 3-D TCAD simulation indicates outperformance of the CFET device for 1-nm node applications. The proposed CFET structure can simplify the manufacturing technology and be fully compatible with current CMOS technology platform.

I. Introduction

The architecture progression of the metal-oxide-semiconductor field-effect transistor (MOSFET) continues to extend Moore’s Law. The evolution from three-dimensional (3-D) Fin field-effect transistors (FinFETs) [1], [2] to stacked nanowires (NWs) gate-all-around (GAA) FETs [3], [4] and nanosheets (NSs) GAAFETs [5], [6], [7] has been used for scaling down. The stacked NWs and NSs GAAFETs offer excellent electrostatic properties and high drive current under fixed footprint. The concept of the complementary FET (CFET) architecture with pFET and nFET stacked on each other was proposed to achieve a further reduction in feature size [8]. CFET has the potential to significantly reduce the standard cell area and is a strong candidate for N1 node mass production. There are two approaches to fabricate CFETs: self-aligned methods [9], [10], [11], [12], [13] and wafer bonding methods [14], [15], [16]. Although the wafer bonding methods demonstrate outstanding performance, additional wafers and separate fabrication of the top and bottom transistors may lead to increased fabrication costs. The 3-D self-aligned method enables direct vertical alignment between the top and bottom transistors simultaneously. However, self-aligned CFETs encounter several challenges. For instance, hole mobility is degraded in the nanosheet structure with (100) surface.