Stochastic-Binary Hybrid Spatial Coding Multiplier for Convolutional Neural Network Accelerator

Convolutional neural networks have remarkable performance in artificial intelligence, although at the cost of computationally demanding processes within a single inference. Simultaneously, the underlying chip process is reaching its constraints as Moore's law diminishes. Stochastic computation, as a hardware-friendly and unconventional approach, can alleviate the burden of sophisticated arithmetic at the circuit level. This work presents a novel stochastic computing (SC) multiplier that employs an extension-uniform approach to create bit sequences without relying on logical gates. In addition, we propose a stochastic-binary domain arithmetic method to achieve low-cost hardware implementation and low power dissipation. The 4n-bit widths are partitioned into n 4-bit widths, with the high-precision components executed in the binary domain and the low-precision components executed in the stochastic domain. Additionally, a hardware-compatible circuit for compensating faults is also introduced. The accelerator on cifar10 using stochastic binary hybrid domain spatial coding (SHSC) multiplier achieves better performance than the fixed-point counterpart, with a 33.7% reduction in area and 23% reduction in power.

I. Introduction

The prescient corollary of Moore's Law is that the performance of microprocessors increases twofold approximately every two years [1]. Nevertheless, the future viability of CMOS technology will be compromised by its physical limitations. The cutting-edge semiconductor technologies, including quantum elements [2], and carbon nanotubes [3], are still far from becoming practically applicable. Therefore, reducing the cost of the chip from the electronic device level is quite challenging. It is crucial to urgently investigate a significant advancement in both the circuit and upper levels.