A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit Reference Frequency Doubling

We propose a ping-pong charge-sharing locking (PP-CSL) PLL which injects charge into the oscillator tank employing complemen-tary charge-sharing capacitors ($C$ shared) during both positive and negative reference clock (fREF) transitions, resulting in an implicit 2x multiplication. The proposed frequency-tracking loop (FTL) and duty-cycle calibrations (DCC) are achieved simultaneously by moni-toring the charge residue on $C$ shared. Implemented in 28 nm CMOS, the ~27 GHz PLL achieves 42 fs of rms jitter while consuming only 14mW with fREF of 250 MHz, leading to FoMjitter-N of -276.6 dB.

Introduction

To support complex modulation schemes (e.g. 1024-QAM) for emerging 5G/6G communications, PLLs with ultra-low jitter (i.e. < 100 fs rms) are required. Recently reported PLLs typically em-ploy a charge-pump or sampling/sub-sampling phase detector with an analog loop filter, but consume large power and/or area [1]–[4]. Alternatively, injection locking (IL) PLLs (see Fig. 1(a)) show promising results but require an additional FTL with accurate timing control to maintain their performance across PVT (process, voltage, temperature). Unlike in the conventional IL techniques (i.e. pulling the oscillator node to an AC ground), the charge-sharing locking (CSL) technique (see Fig. 1(b) [7]) allows to digitally control (via a DAC) the charge on to be injected into the LC tank, which can be readily extended for a fractional-N operation. The charge residue on , left after the injection pulse, can be sensed for the frequency error without any timing issues. However, [7] still requires manual calibration for PVT-sensitive injection pulse width for trading -off the optimum jitter and spur performance, since the narrow pulse may suffer from the limited time for the injection, resulting in lower bandwidth, while a wider pulse would result in a longer time in which the LC tank is loaded by . This issue is becoming more challenging at mm-wave. Furthermore, [7] requires precise control of the DAC to ensure that the voltage on is always aligned with the common-mode (CM) voltage of the oscillator. Fig. 1

Conceptual diagrams of (a) conventional injection locking and (b) charge-sharing locking PLLs. (c) Proposed ping-pong charge-sharing locking (PP-CSL) PLL.