A 1.1pJ/b/Lane, 1.8Tb/s Chiplet Over XSR-MCM Channels Using 113Gb/s PAM-4 Transceiver with Signal Equalization and Envelope Adaptation Using TX-FFE in 5nm CMOS

This paper uses 113Gb/s PAM4 transceiver in 5nm CMOS to demonstrate a 1.8Tb/s chiplet, over die-to-die extremely short-reach (XSR) intra-package links, in a 8-port configuration. The 16-channels range from 1dB-12dB of loss at $F_{baud}/2$. The chiplet performance over these channels is better than $BER < 10^{-9}$, while consuming $<$ 1.1pJ/b power and 0.22mm² area per lane.