Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5)

In this paper, we make a thermal-aware block-level PPA comparison study for nanosheet transistors (NSFET) and complementary field effect transistors (CFET), expected to be used in future Angstrom nodes, namely A10 and AS respectively. We report block-level scaling results from AI0 to AS node on an open-source many-core architecture: 2.5% increase in Fmax, 25% reduction in power, 27% reduction in energy per cycle, achieved with 35% area reduction and a consequent increase in power density by 15% under nominal 0.7V/2SC. The PPA analysis methodology has been augmented with a fast package-level thermal simulator to enable early self-consistent thermal estimation that accounts for exponential leakage power increase with temperature, which is important for dynamic thermal management (DTM) applications. The analysis reveals a reduction of 64mV in Vdd and 10% in frequency required for A5 node to maintain same Tj,max as Al 0 node operating at 0. 7V, still resulting in a 40% gain in system throughput.