64-Bit High Speed Counter with Galois LFSR

High-speed counters are very essential in modern world technology to work digital devices very quickly but existing counters cannot achieve high clock rate. This paper describes the design of the high-speed counter technique by considering 64-bit counter into two sub sections. The first sub section is a 6bit Galois LFSR counter along with an LUT used to covert Galois LFSR state to binary state. The second section is 58 bit binary counter. The propagation delay of this counter only depends on Galois LFSR. So, this 64-bit counter will work on clock rate of Galois LFSR which is very high as compared with older counters. Finally, It’s speed does not depend on the counter size, like a conventional binary counter and it requires 5 number of flipflops less as compared to novel LFSR state extension method which leads to reduction in area and lesser power dissipation. The functionality of this design was implemented in modelsim and synthesized in quartus prime.