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CHERI: Hardware-Enabled C/C++ Memory Protection at Scale | IEEE Journals & Magazine | IEEE Xplore
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Journals & Magazines >IEEE Security & Privacy >Volume: 22 Issue: 4

CHERI: Hardware-Enabled C/C++ Memory Protection at Scale

Robert N. M. Watson; David Chisnall; Jessica Clarke; Brooks Davis; Nathaniel Wesley Filardo; Ben Laurie
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Under a Creative Commons License

Abstract:

The memory-safe Capability Hardware Enhanced RISC Instructions (CHERI) C and C++ languages build on architectural capabilities in the CHERI protection model. With the dev...Show More

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Abstract:

The memory-safe Capability Hardware Enhanced RISC Instructions (CHERI) C and C++ languages build on architectural capabilities in the CHERI protection model. With the development of two industrial CHERI-enabled processors, Arm’s Morello and Microsoft’s CHERIoT, CHERI may offer the fastest path to widely deployed memory safety.
Published in: IEEE Security & Privacy ( Volume: 22, Issue: 4, July-Aug. 2024)
Page(s): 50 - 61
Date of Publication: 21 June 2024

ISSN Information:

DOI: 10.1109/MSEC.2024.3396701

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