A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage

This article presents a 12-bit 1.5-GS/s single-channel pipelined successive approximation register (SAR) analog-to-digital converter (ADC). The ADC leverages a pipelined residue amplification (RA) stage scheme, early quantization technique, and fast differential ring amplifier (ringamp) to achieve high speed and high power efficiency simultaneously. The pipelined RA stage scheme allows the RA and SAR conversion to run in parallel for a fast pipelining operation and a relaxed residue amplifier’s bandwidth requirement, thus alleviating the speed bottleneck of the pipelined SAR ADCs. The early quantization technique reduces the timing budget of the SAR conversion phase, thereby further improving the ADC speed. The differential ringamp with a short settling time and low common-mode gain guarantees the high accuracy and high speed of the critical RA. Furthermore, a flexible digital-to-analog-converter (DAC) topology combining the scaling capacitor and bridge capacitor is employed to align the quantization range avoiding large overheads. The prototype ADC was fabricated in a 28-nm CMOS process and consumes 21.3 mW at 1.5 GS/s. The signal-to-noise-and-distortion-ratio (SNDR) and spurious-free dynamic range (SFDR) are 58.5 and 74.5 dB with a Nyquist input, respectively, achieving a Walden figure-of-merit (FoM) of 20.7 fJ/conversion step and a Schreier FoM of 164 dB.