Exploring Variable Latency Dividers in Vector Hardware Accelerators

Efficient hardware implementation of integer division remains one of the most significant challenges in the design of vector hardware accelerators, particularly in achieving a balance between performance and hardware overhead. This work uses the RISC-V Klessydra-T13 Vector Coprocessor Unit as a case study to explore the impact of variable latency division architectures for vector hardware accelerators. We analyze existing designs in the literature to identify the most effective approach, detailing the whole integration process with new instructions for supporting vector divisions in the RISC-V custom instruction set and optimizing the implementation for the target accelerator by exploiting hardware reuse. We also provide real-world computation kernels and Monte Carlo simulations to demonstrate how a variable latency divider can significantly improve the division time over traditional methods with negligible hardware overhead.

I. Introduction

Vector hardware accelerators are specialized computing units designed to process vector operations, optimizing the execution time in conjunction with technology scaling and energy efficiency demands of heavy computational workloads in Artificial Intelligence (AI) and High-Performance Computing (HPC) applications [1]–[3]. They are usually organized in multiple vector lanes equipped with arithmetic functional units that allow the parallel execution of the same instruction on different data in a Single Instruction Multiple Data (SIMD) fashion.