Design of a Linearized Power-Efficient Dynamic Amplifier in 22nm FDSOI

Dynamic amplifiers are emerging as a popular alternative to conventional operational amplifiers due to their high power-efficiency, albeit at the cost of linearity performance. We describe a dynamic amplifier that achieves both good linearity and low power with the help of an analog linearization technique based on the cancellation of expanding and compressing non-linearities inherent in the input transistors. A linearized dynamic amplifier is designed based on this technique in the GobalFoundries 22nm FDSOI process, leveraging its back-gate biasing feature. Our simulations demonstrate a 22dB of improvement in THD while incurring an negligible power overhead. Additionally, we proposed and implemented a calibration method to automatically optimize the amplifier’s performance.

I. Introduction

Amplifiers have always been a crucial and fundamental building block in analog-mixed signal designs. For example, operational amplifiers have been traditionally used inside feedback loops in the residue amplification stages of pipeline ADCs. However, designing this critical component to achieve low power consumption while maintaining a high conversion speed above 1 GS/s proves challenging.