Design of a Linearized Power-Efficient Dynamic Amplifier in 22nm FDSOI

Dynamic amplifiers are emerging as a popular alternative to conventional operational amplifiers due to their high power-efficiency, albeit at the cost of linearity performance. We describe a dynamic amplifier that achieves both good linearity and low power with the help of an analog linearization technique based on the cancellation of expanding and compressing non-linearities inherent in the input transistors. A linearized dynamic amplifier is designed based on this technique in the GobalFoundries 22nm FDSOI process, leveraging its back-gate biasing feature. Our simulations demonstrate a 22dB of improvement in THD while incurring an negligible power overhead. Additionally, we proposed and implemented a calibration method to automatically optimize the amplifier’s performance.