Abstract:
This paper proposes an approach based on oversampling and noise-shaping mechanisms to mitigate the implementation complexity of variable delay lines for mixed-signal cali...Show MoreMetadata
Abstract:
This paper proposes an approach based on oversampling and noise-shaping mechanisms to mitigate the implementation complexity of variable delay lines for mixed-signal calibration of timing-skew mismatch in time-interleaving ADCs. The proposed technique pushes the error (introduced by increasing the delay steps) outside the operating frequencies. Our method is more appropriate for noise-shaping time-interleaved ADCs since they are band-limited. However, the proposed method permits the utilization of either the high-frequency or low-frequency zones. This approach avoids utilizing complex clock routing methods. Also, it does not restrict the number of sub-ADCs. The proposed method is verified by behavioral simulations with MATLAB/Simulink. The mean of the spurious-free dynamic range (SFDR) is respectively enhanced by 11.64 dB and 17.72 dB for the low-frequency and high-frequency zones.
Date of Conference: 19-22 May 2024
Date Added to IEEE Xplore: 02 July 2024
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Electrical Engineering Department, Polytechnique Montréal, Montréal, Canada
Electrical Engineering Department, Polytechnique Montréal, Montréal, Canada
Analog IC Department, Ciena Corporation, Ottawa, Canada
Analog IC Department, Ciena Corporation, Ottawa, Canada
Analog IC Department, Ciena Corporation, Ottawa, Canada
Electrical Engineering Department, Polytechnique Montréal, Montréal, Canada
Electrical Engineering Department, Polytechnique Montréal, Montréal, Canada
Electrical Engineering Department, Polytechnique Montréal, Montréal, Canada
Analog IC Department, Ciena Corporation, Ottawa, Canada
Analog IC Department, Ciena Corporation, Ottawa, Canada
Analog IC Department, Ciena Corporation, Ottawa, Canada
Electrical Engineering Department, Polytechnique Montréal, Montréal, Canada