Per-Instruction Cycle Stacks through Time-Proportional Event Analysis

Understanding what applications spend time on and why is critical for effective performance optimization. Unfortunately, current state-of-the-art performance analysis tools are generally unable to provide this information. The fundamental reason is that they lack time-proportionality, i.e., in many cases, they do not attribute execution time to the instructions and performance events that the architecture is exposing the latency of. Time-proportional Event Analysis (TEA) creates Per-Instruction Cycle Stacks (PICS), which clearly and accurately explain what the application spends time on and why at the level of individual static instructions. TEA requires executing the application only once, is accurate (average error of 2.1%), and its hardware implementation incurs negligible runtime, power, and area overheads of 1.1%, 0.1%, and 249 bits per core, respectively.