Improving P-Doped DBRs Operation at Cryogenic Temperatures: Investigating Different Mirror Geometry

The use of vertical-cavity-surface-emitting lasers with ability to operate at cryogenic temperatures (Cryo-VCSELs) is a promising path to implement optical data links between superconducting processors maintained in cryogenic environments (4 K range) and room temperature (RT) computing hardware. In order to achieve energy-efficient operation of a cryo-VCSEL, whether by passing current through the mirrors or utilizing intra-cavity contacts, a critical bottleneck for improving the operation is related to the p-doped distribute Bragg Reflectors (DBRs). This is because holes exhibit lower mobility and lower thermal conductivity compared to their n-side counterparts. To determine the actual temperature of an operating p-doped DBR and its impact on the behavior of the DBRs and the cryo-VCSEL, a thermal simulation using the finite-element method was conducted and validated with experimental results. Furthermore, we explored different mirror geometries to optimize both current flow and the growth complexity of the DBR. DBR layers with various interface shapes, such as uni-parabolic grading and three to five steps with different Al mole fractions, have been investigated. As a result of the study, we achieved more efficient operation at cryogenic temperatures, with a 60% reduction of the series resistance and a 39% reduction of the voltage penalty related to the p-doped DBR.

SECTION I. Introduction

Scaling down the feature size of CMOS technology to accommodate the exponential growth of users by increasing the computational power, has resulted in unsustainable growth in power consumption within data centers and high-performance computers (HPC). The thermal limits imposed by CMOS technology have resulted in a need to develop alternative computational techniques. Among numerous candidates, superconducting processors based on single flux quantum (SFQ) technology have garnered considerable interest [1], [2], [3], [4]. They have a good power efficiency even when accounting for cooling power consumption [1]. However, despite significant advancements in SFQ technology, a critical bottleneck remains for scaling up superconducting-based processors when it comes to availability of energy-efficient high-speed links between the low temperature environments where the cryogenic computers are located, and the room temperature (RT) user side and control units. To this end, high-speed and low power vertical-cavity-surface-emitting lasers with ability to operate at cryogenic temperature (cryo-VCSELs) are seen as a solution [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16].

VCSELs are widely used for efficient data communication at elevated temperature owing to their low threshold current and high-speed operation. However, as temperatures goes down to extremely low values, the physical parameters like refractive index of the layers, thermal conductivity, mobility, bandgap, and activated dopants will change [17], [18], [19], [20], leading to new sets of constrains for optimal designs. One of the challenges in achieving a high-performance cryo-VCSEL lies in its p-doped DBR mirrors, which should pass current with minimal resistance. While it is possible to circumvent the need for using p-DBRs by implementing the double-intra-cavity device architecture [21], [22], this technique introduces additional complexity to the process flow (critical alignment, etching-stop difficulties, and the need of insulators to decrease the capacitance between contacts for high-speed operation). To enhance the functionality of VCSELs and circumvent the problems with the p-doped DBRs, tunnel-junction (TJ) VCSELs [23], [24], [25] could potentially serve as a solution. However, due to the partial ionization of the dopant at extremely low temperatures [26], tunneling suffers from a low level of ionized dopants, which can pose challenges for carrier conversion. Additionally, the fabrication process for TJ-VCSELs is known to be complex. On the other hand, passing current through the mirrors leads to more uniform current injection, and to some extent, we can leverage the heat generated inside the device.

In this work, we address the challenges posed by p-doped DBRs, particularly regarding the heterojunction band discontinuities at each interface, which impede the current flow to the active region. A uni-parabolic grading at each heterojunction interface, results in a noticeable reduction in resistance. Other mirror geometries that are comparable to uni-parabolically graded mirrors but are also more practical and easier to fabricate are also investigated. The details of the designs considered are included in Section II. Then in Section III, we develop a thermal analysis and modify the thermal conductivity model to match the simulation results with the electrical characteristics (I-V dependence) of experimental p-DBRs. We discuss how the temperature of the operating device changes relative to the temperature of the cryogenic chamber. The finite-element model is used to examine the actual temperature of an operational device and to determine the minimum substrate thickness needed to isolate the device from the cryogenic cooling stage, as well as the steady-state temperature of the device while it is kept at extremely low temperatures. To address the voltage-drop across multiple heterojunctions in DBRs, various bandgap engineering techniques have been implemented to flatten the valence band. In Section IV, we introduce different mirror interface structure and investigate their impact on the voltage drop-off across the DBRs. Finally, we compare the results for the structures studied and discuss the advantageous role of Al content in AlGaAs.

SECTION II. Structure Design

Our study considered the design variation of the doping profile in the AlGaAs layers of the p-type DBR. The experimental structure of the p-DBRs comprised 15 pairs of p-AlGaAs layers, with the highest-index corresponding to an Al composition of 12%, and the low-index corresponding to and Al composition of 90%. The thickness of one DBR period was 140nm. In this study we fabricated and measured two p-DBR samples: Sample 1, and Sample 2. The transition between the high and low refractive index region was graded. The specifications for one period of these two designs considered are detailed in Table I.

TABLE I P-DBRs Epilayers Specification

The parabolic grading design and step-grading designs utilized in the studies are visually depicted in Fig. 1. Specifically, for comparison, Fig. 1(b) illustrates the valence band of five-step interfaces alongside Sample 1, as well as the uni-parabolic geometries competing with the uni-parabolic grading counterpart. As shown in Fig. 1(b), the potential barrier decreases in five-step interfaces compared to Sample 1, which incorporates three steps, but it remains twice as high as the uni-parabolic potential barrier. However, in step-grading, tunneling also plays a significant role in current flow since carriers can tunnel through the kinks in heterojunctions, making this structure comparable to the uni-parabolic grading. Further discussion will be provided in Section V.

Fig. 1.

(a) The band diagram of one period of a uni-parabolically graded, three steps interfaces, and five steps interfaces p-DBR. (b) Zoomed view of the valance band of the three structures.

Although these modifications on the valance band are mainly targeted for low temperatures, the design consideration can be also beneficial for devices operating at room temperature (RT) since these intermediate layers make the valance band smoother and increase the intra-band tunneling effect and thermionic emission. The modifications have less impact at RT because carriers (holes in this study) have higher thermal energy to overcome the potential barriers. Moreover, these modifications can be also applied to the n-doped DBRs to further improve the electrical resistance. Since electrons have a higher mobility in most of semiconductors, the probability of tunneling through the same potential barrier is higher due to their smaller effective mass compared to holes. In addition, it is much easier to grow Si-doped AlGaAs with a high donor level than reach a high acceptor level in Be-doped AlGaAs. Therefore, the n-doped DBR is not considered a limiting factor in the design of the VCSELs.

SECTION III. Thermal Analysis

For a cryo-VCSEL placed in a cryogenic environment, e.g., near 4.2K, it is essential to determine the actual operating temperature of the device under current injection. The p-type AlGaAs/GaAs mirror usually has an electrical resistance that is approximately an order of magnitude greater than that of the n-type mirror, resulting in enhanced voltage drop and resistive heating compared to n-type regions. Hence, determining the actual temperature of a p-DBR under bias at different temperatures is important for the actual operation.

To gain a profound understanding of the thermal behavior in the p-DBRs, a systematic theoretical thermal analysis using a heat dissipation model is necessary. This analysis has the potential to guide the optimization of the device structure for improved thermal management [27], [28], [29], [30]. Thermal analysis, employing the finite element method (FEM), was carried out to model heat transport in the VCSEL structure using the commercial COMSOL Multiphysics software. The examination of devices involved an exploration of the temperature profile, temperature rise time, and thermal resistivity (r) by integrating experimentally derived heat source values into the thermal simulation. To obtain the temperature distribution, the time-dependent heat-flux equations were solved via the finite-element method. The equations are as follows [29], [30]: \begin{align*} &\rho {{c}_p}\frac{{\partial T}}{{\partial t}} + \rho {{c}_p}\nabla T\ = \ \nabla \cdot \left( {\kappa \nabla T} \right) + {{Q}_{tot}}, \tag{1}\\ &\kappa \nabla T\ = {{q}_0}\ + h\left( {{{T}_{inf}} - T} \right) + \varepsilon \sigma \left( {T_{amb}^4 - {{T}^4}} \right), \tag{2} \end{align*} where, ${{c}_p}$ is the specific heat, $\rho $ is the density of the material, $\kappa $ is lattice thermal conductivity, ${{Q}_{tot}}$ is the heat source (which is the total electrical power dissipated in the device at the center the of DBRs which can be primarily regarded as Joule heating), ${{q}_0}$ is inward heat flux, $h$ is heat transfer coefficient, $T$ is initial temperature, ${{T}_{inf}}$ is ambient bulk temperature, ${{T}_{amb}}$ is temperature of the surrounding radiation environment, $\varepsilon $ is emissivity of the surface, and $\sigma $ is Stefan–Boltzmann constant.

A significant portion of the overall heat budget in the VCSEL structure is attributed to the Joule heating generated by the p-DBRs. Therefore, optimizing the Joule heating produced by the p-DBRs is an essential measure to enhance the overall performance of the device. As the current flows through the p-DBRs, the primary source of heat is generated through Joule heating [31]. While there are non-radiative recombination mechanisms, such as Shockley-Read-Hall (SRH) recombination, Auger recombination, and other non-radiative pathways, that may contribute to heat generation in the device, we are examining p-doped DBR samples. In these samples, we do not expect radiative recombination. Additionally, since only holes play the primary role in the current conduction, the likelihood of non-radiative recombinations is relatively low. Consequently, nearly all the supplied electrical power can be regarded as being transformed into heat [32] whether through Joule heating or non-radiative mechanisms. Therefore, we can derive an estimate for the heat source value based on the electrical power consumed in the experimental measurements of these DBRs.

One of the most important parameters that needs to be assigned in the heat-flux equations is thermal conductivity (κ), which is temperature and material dependent. It also changes with the doping levels and the type of doping as well. However, there is still a lack of studies on the thermal conductivity for a variety of materials with different doping types and levels at low temperatures. Hence, we used the thermal conductivity value reported in [20], [33] for GaAs and modified it with the model presented in [34] for AlGaAs in an iterative way that the electrical simulation results fit with the experimental I-V characteristics of the p-doped DBR samples. Instead of calculating the conductivity, this is obtained by matching the calculated current-voltage relation with the measured one. First, at the lowest temperature possible for the software we calculate the I-V curve with the original structure. Then we find the closest experimental data to the first guess and try to fit the data using the thin interface layers as a fitting parameter with different thickness. This fitting parameter is compensating for the tunneling effects at each barrier. The fitting procedure was then repeated for the highest temperature and the interface layer thickness, doping levels, and mesa radius were changed in such a way that the two I-V curves and differential resistance of highest and lowest possible temperatures fit with the experimental data. The fitting parameters for the two samples are provided in Table II. Then, we change the temperature in order to fit the new simulated curve with the next experimental curve and extract the temperature difference. We took the fitted simulation values for the temperature as the operating temperature value and the corresponding temperature of the experiment as the temperature of the cooling stage. These cooling stage temperature values and operating temperature values were fed into a heat transfer model in COMSOL as initial and final temperature of an operational p-doped DBR. Then we could extract acceptable mean values for thermal conductivity of the p-doped DBR structure as depicted in Fig. 2(a).

TABLE II Fitting Parameters for Two Samples

Fig. 2.

(a) Extracted thermal conductivity for different Al mole fraction (x in Al_xGa_1-xAs) at temperature between 100 K and 10 K. The layers are Be doped with average doping level of 5.77e+18 (sample #1). The inset shows the parabolic dependency of thermal conductivity with respect to Al mole fraction [34] at T = 40 K. (b) Thermal resistivity (the inverse of thermal conductivity) of DBR constituents and the total dissipated electrical power.

In multilayer thin-film structures, thermal conductivity differs from that of bulk material due to increased scattering by interface phonons [27]. This discrepancy is partly ascribed to thermal boundary resistance (TBR) at each interface, leading to a reduction in the thermal conductivity of the material. The thermal boundary resistance at each interface differs between two structures due to variations in material properties such as acoustic impedance mismatches, phonon scattering mechanisms, and the presence of interfacial defects or roughness. Different materials or different compositions within the same material system can lead to variations in how thermal energy is transmitted across interfaces, affecting the overall thermal conductance. [35], [36]. But in this study, due to lack of many temperature-dependent parameters contributing in TBR, the effect of TBR has not been included in the model. To ensure accuracy in the calculations, effective thermal conductivities with anisotropy were applied to thin multilayers, featuring distinct values in lateral and vertical directions, as demonstrated in the equations below [31]. \begin{equation*} \left\{ {\begin{array}{l} {{{\kappa }_l} = \frac{{{{d}_1}{{\kappa }_1} + {{d}_2}{{\kappa }_2}}}{{{{d}_1} + {{d}_2}}}\ }\\ {{{\kappa }_v} = \frac{{{{d}_1} + {{d}_2}}}{{{{d}_1}/{{\kappa }_1} + {{d}_2}/{{\kappa }_2}}}\ } \end{array}} \right. \tag{3} \end{equation*} where ${{\kappa }_l}$ is lateral thermal conductivity, ${{\kappa }_v}$ is vertical thermal conductivity, ${{\kappa }_1}$ (${{\kappa }_2}$) and ${{d}_1}$ (${{d}_2}$) are the thermal conductivity and thickness for layer 1 (layer 2), respectively. Except for the DBRs region, isotropic thermal conductivity values were considered. The extracted thermal conductivity is the mean thermal conductivity value of mainly two alternating layers with the Al content of 12 percent and 90 percent respectively. The thermal conductivity values for AlGaAs with the Al content of 12 percent and 90 are very close to each other [36]. Hence, we can assume one monolithic material with Al mole fraction of 12 percent for the whole DBRs and then find the thermal conductivity of layers with any desired Al mole fraction [36].

Based on the heat transfer model, the temperature difference across the material due to conduction is proportional to the heat transfer per unit time and inverse of thermal conductivity (i.e., $\Delta T \propto Q/\kappa $). The thermal conductivity, that characterizes the material property how well heat is dissipated from the active area, and Joule heating that governs the heat generation in the active region are important parameters. Thus, these two parameters play an important role in the device heating up: first, the inverse of thermal conductivity or it can be addressed as thermal resistivity, and second, the heat power generated inside the device due to Joule heating. In Fig. 2(b), it can be observed how the dissipated electrical power and the thermal resistivity of bulk GaAs, as well as the lateral and vertical resistivity of the p-DBR layers, vary. The lateral and vertical thermal resistivity mentioned here are the inverse of the respective conductivities ($\ {{r}_l} = \ \kappa _l^{ - 1}$and $\ {{r}_v} = \ \kappa _v^{ - 1}$), indicating resistance to heat flow in parallel and perpendicular directions to the surface of material.

The dashed black line in Fig. 2(b) represents the thermal resistivity of GaAs ($r$) at different temperatures. The blue and purple lines correspond to the lateral (${{r}_l}$) and the vertical thermal resistivity (${{r}_v}$) of alternative layers of Al_0.12Ga_0.88As and Al_0.9Ga_0.1As, respectively. The dashed turquoise line shows the Joule heating (${{P}_e}$) generated inside the p-DBR. To see how the dissipated electrical power related to the Joule heating, the electrical resistance versus temperature at different current bias depicted in the inset.

The Joule heating generated inside the device exponentially increases with the decrease of the temperature, due to the increasing electrical resistance as it is illustrated in the inset of Fig. 2(b). This increase is attributed to the exponential decline in the probability of carriers (holes in this study) to overcome potential barrier with decreasing temperature [37]; this probability is proportional to the Boltzmann factor i.e., $I \propto {{e}^{ - q\Phi ( {{{V}_{app}}} )/kT}}$ where the $\Phi ( {{{V}_{app}}} )$ is the potential barriers in the valance band between each heterojunction and, it changes with the change of applied voltage. Therefore, at low temperatures the probability of holes to overcome potential barriers decreases exponentially with respect to the decreasing temperature. This would result in increased electrical power injected into the device to achieve the same amount of current as at room temperature. From the inset plot of Fig. 2(b) that shows the measured electrical resistance as a function of temperature, it is evident that the electrical resistance rises exponentially as the temperature declines, as anticipated previously. A roll-over occurs in the electrical resistance at very low temperature values which is attributed to the rise in temperature within the device caused by the low conductivity and the higher conversion of electrical power to heat. Fig. 2(b) indicates that at extremely low temperatures both the thermal resistivity and the heat generated inside the device are high, resulting in a rise in the temperature to noticeable values. In Fig. 3 and in the inset, it can be seen how the temperature changes as we inject current into the device at different temperatures. The inset shows how the increase in temperature ($\Delta T$) is proportional to the product of the dissipated electrical power and thermal resistivity (${{P}_e} \times r$).

Fig. 3.

The time dependency of an operating p-DBR reveals a 500 ns temperature time constant and a 4 μs rising time, with approximately a 23 K difference between the operating and non-operating device at a 10 K chamber temperature (T0). The inset illustrates the proportionality of the increase in temperature (the blue line) with the product of Joule heating generated in the device and the thermal resistivity (dash red line). It indicates a minimum for temperature rise at around 80 K.

In Fig. 4, a schematic of an operating p-DBR is presented. It can be observed that the local temperature rises to much higher values than the substrate itself, which is attached to the cooling stage of the cryostat, assumed to stay at a fixed temperature.

Fig. 4.

(a) A schematic picture of an operating p-doped DBR that is thermally insulated from the top side (thermal radiation is assumed to be small compared to thermal conduction) and contacted to the cryogenic plate from the bottom of substrate. (b) A zoomed-out view of the device. The substrate height is 300 μm, mesa height, and mesa radius are 3.38 μm, and 5 μm respectively.

The thick substrate partially isolates the device from the cooling stage at the bottom of the substrate. Therefore, we can adjust the actual device temperature based on the substrate thickness for different applications. We can also design devices for operation below Kelvin (<1K) temperatures with less concern for adding thermal load to other parts of the circuit by selecting an appropriate thickness for the substrate.

We measured the I-V curve of the p-doped DBRs at different temperatures using a pulse current of 1kHz with a 5% duty cycle (i.e., the current injected into the device around 50 μs). In Fig. 4, two cases were shown, where the temperature of a DBR placed in a 10 K chamber rises to 33 K and in an 80 K chamber rises to 89K, both in less than 5 μs. Now, we understand that the device temperature increases to values higher than the cryogenic chamber temperature shortly after turning it on and before the pulse ends. Therefore, the operating temperature is higher than the turned-off device. We can calibrate our simulation with this temperature difference between the operating and non-operating device.

For an operating p-DBR attached to a 10 K substrate, Fig. 5 depicts the steady-state temperature of the device and the temperature of a point close to the bottom of the substrate concerning the substrate thickness. It is shown that for a device maintained at a 10 K cooling stage, the minimum substrate thickness for isolating the device from the sub-mount is around ∼100 μm. Of course, this value will change at lower temperatures.

Fig. 5.

The red line represents the steady-state temperature of operating p-doped DBRs, while the blue line depicts the temperature trend of a point close to the substrate, which is attached to the cooling stage, with respect to the substrate thickness. The cooling stage is maintained at 10 K.

SECTION IV. Electrical Analysis

Although the doping levels mentioned in Table I can be used for both cryogenic and room temperatures, their main selection criterion is to ensure a flat valance band at RT. Because the ionized dopant decreases [26] as the temperature decreases for operation at cryogenic conditions, we can dope the layers to higher values without much concern about the free carrier absorption (FCA). To understand these aspects, we performed a hetero-structure simulation using Harold by Photon Design for layers specified in Table I and utilized the temperature results discussed in the previous section. The results are summarized in Fig. 6(a).

Fig. 6.

(a) The valance band diagram of a single period of the p-doped (based on sample 1) DBR biased at V = 0.2 (V) at three different temperatures. (b) The I-V curves for these three different temperatures with and without considering tunneling in the model. The effect of tunneling is notable at lower temperatures.

When the device operates at room temperature most of the dopant atoms are ionized, resulting in a wide probability distribution of holes below the Fermi level compared to when the device is kept at low temperature. As temperature decreases, on one hand, the dopants become partially ionized which makes the potential barrier higher at low temperatures as illustrated in Fig. 6(a). On the other hand, at lower temperature as discussed above, the hole probability distribution become closer to the valance band; hence, the possibility of diffusion of holes over the potential barriers at the heterojunction interface become even worse which can be seen in the Fig. 6(b). In a heterojunction, when a thin layer of potential barrier forms due to band bending, if the barrier width and/or barrier height are small enough, it can lead to a substantial increase in the current density as charge carriers can engage in quantum tunneling across the barrier as depicted in Fig. 6(a), making a significant impact on the current flow.

To see the effect of tunneling on the current flow, a simulation has been done in COMSOL Multiphysics employing a WKB¹ tunneling model. The influence of tunneling can be included as an additional factor [38] to the drift-diffusion model, denoted as δ, which scales the current density scaled by a factor of (1+δ). This incorporation is achieved by employing the WKB approximation. At low temperatures, since the holes cannot easily diffuse over the barrier, then the contribution of tunneling in the current flow becomes noticeable as it is observable in Fig. 6(b), while at high temperatures the tunneling contribution in the simulated structures is not high enough compared with the drift-diffusion terms.

The tunneling is less probable for holes due to the fact that holes have heavier effective mass than electrons in most of semiconductors. Electrons occupy a single band, whereas holes are distributed across two bands: the heavy-hole band and the light-hole band. This multiband characteristic of valence bands introduces complexity to tunneling phenomena, as there needs to be a blending of states with varying effective masses. The influence of inter-band mixing is more pronounced for holes compared to electrons due to the presence of multiple bands [39]. Consequently, in hole tunneling, there must be tunneling routes between bands with differing effective masses (e.g., hh → lh or lh → hh) in addition to those within the same bands. Since we could not include all the inter-band mixing paths for holes in the WKB model of COMSOL, only the contribution of heavy-holes in tunneling current was taken into account in the model. However, COMSOL shows reliable results for one period of DBRs. To simulate the whole DBRs structure, we utilize Harold but then, since Harold does not incorporate the intra-band tunneling model for holes, we added thin layers of a few nanometers at each interface to compensate for the WKB tunneling model. These layers can roughly include all the intra-band tunneling effects. Keeping in mind these two parameters, i.e., the temperature and the thin interface layers, we were able to fit the simulation data with the experimental results as shown in Fig. 7.

Fig. 7.

Fitted simulated I-V curves at different temperatures ranging from 10 K to 150 K with the Sample 2 experimental results. There is a good agreement between the simulation results and the experimental results.

In Fig. 8(a) and (b), the I-V characteristics and differential resistance at different temperatures for Sample 1 are illustrated, along with the corresponding simulation results. As evident, the simulation results align with the experimental results using the fitting parameters in Table I. Now the simulator is calibrated based on the characteristics of Sample 1.

Fig. 8.

(a) The I-V characteristic and the differential resistance of Sample 1 at temperatures between 10 K to 150 K. (b) The simulation results of the corresponding sample. The dashed lines are related to the voltage of the device and the lines corresponding to the differential resistance.

In the next section, we are going to propose different DBRs with different geometries and make a comparison between them to find a proper design for an energy-efficient cryo-VCSEL.

A. Proposed p-Doped DBRs With Different Geometry

To achieve a flat valence band at heterojunction interfaces, various attempts have been made, including digital alloy linear grading, continuous linear grading, employing low-contrast interfaces, and parabolically and uni-parabolically grading with modulation doping [40], [41], [42]. Among these techniques, the uni-parabolically grading technique with modulation doping has the most advantages [43]. However, Molecular Beam Epitaxy (MBE) systems encounter difficulties to create graded alloy composition, especially when using digital alloys that require frequent changes in growth conditions. When trying to create a smoothly varying composition gradient in alloys, especially with digital alloys that demand rapid adjustments to growth conditions, MBE machines encounter mechanical constraints. These challenges impose mechanical limitations on Molecular Beam Epitaxy (MBE) machines with shutters that need frequent opening and closing. These constraints make it difficult to effectively grow structures with the required characteristics. Many MBE machines do not provide the ideal support for this specific type of alloy composition grading.

In this section, we employed three different configurations for the intermediate layers between the low and high Al content layers of AlGaAs. The first considered structure consists of a 35 nm uni-parabolically graded layer with modulation doping to compensate for the valence band potential barriers. In this study we also considered two other designs: one with three step-like interface layers of 7nm, and the other one with four step-like interface layers of 5nm. The additional interface layers to the ones used in the base structures (Table II - Sample 1) are 7 nm of Al_0.5Ga_0.5As in the structure with four interface layers and for five interface layers are 5 nm layers of Al_0.5Ga_0.5As and Al_0.8Ga_0.2As.

In Fig. 9, the I-V characteristics, and the differential resistances of these three configurations at different temperatures are provided.

Fig. 9.

(a) The lines show voltage versus current for a p-DBR with uni-parabolically graded interfaces and the dash-lines are representing the derivatives (resistance). (b) depicts with four and (c) with five step-like interfaces p-DBR I-V and resistance.

As predicted, the DBR layers with uni-parabolically graded interfaces (Fig. 9(a)) show better electrical behavior due to a smoother valence band. The valence band kinks are mitigated due to the graded interfaces and modulation doping, resulting in lower potential barriers and higher current at lower temperatures. On the other hand, the two other structures with more step layers compared to the base structures (i.e., Samples 1) can take advantage of having smoother valence band kinks and intra-band tunneling through the narrow potential barriers of the thin interface layers. From the I-V curves depicted in Fig. 9 with a color gradient representing varying temperatures across all three graphs, it is evident that at lower temperatures the uni-parabolically graded p-doped DBRs exhibit comparatively lesser voltage penalty. While the voltage penalty and resistance depicted in Fig. 9(b) and (c) demonstrate some improvement compared to the base structures presented in Figs. 7 and 8, there is still potential for enhancement, which we will address in the next section.

The figures demonstrate that carriers can flow easily within the device at high temperatures due to their sufficient thermal energy (${{k}_B}T$). In contrast, at lower temperatures, carriers lack the required thermal energy to overcome barriers through thermal means. However, even at low temperatures, carriers can employ the intra-band tunneling effect to navigate through the barriers, which is more common in the DBRs with step-like interfaces (e.g., Fig. 9(b) and (c)). From the dashed lines depicted in Fig. 9 representing the differential resistance, it is observed that the uni-parabolically graded design exhibits lower resistance compared to the other structures. In the subsequent section, efforts will be made to minimize the voltage and differential resistance in the DBRs with step-like interface layers to bring them in line with the performance of the uni-parabolically graded structure.

B. p-DBRs With Low Refractive-Index Contrast

To enhance the efficiency of the step-like interface p-DBRs, in contrast with high-contrast (HC) DBRs, which incorporates Al_0.12Ga_0.88As/ Al_0.9Ga_0.1As layers as high/ low refractive index respectively, we introduce low-contrast (LC) DBR layers by implementing Al_0.18Ga_0.82As for the high-index side and Al_0.85Ga_0.15As for the low-index side. Additionally, to mitigate the voltage penalty between the GaAs conducting layer and the first layer of p-DBR (i.e., Al_0.18Ga_0.82As) we implemented a thin layer of Al_0.12Ga_0.88As only for the first period of these proposed p-DBRs. Since the refractive index contrast is lower in this configuration than the base structure, we added two more periods to the existing p-DBRs (17 pairs in total) to compensate for the reflectivity drop of the mirror. The Al compositions for the four-steps configuration are 18%, 30%, 42%, 67%, and 85%, and for the five-steps configuration are 18%, 30%, 42%, 67%, 80%, and 85%.

The optical performance of these low-contrast DBRs are compared in Fig. 10 with reflectance values of the base structure (Sample 1). It is evident that by incorporating two additional periods into the LC-DBRs, we can achieve nearly identical optical performance to that of the HC-DBRs. This is also true for other proposed structures. This prompts the question of how these extra layers will impact the electrical performance of the device. In the subsequent section, we will examine the electrical behavior of all proposed structures to gain a deeper understanding of device performance.

Fig. 10.

(a) The reflectance at various wavelengths is examined for four DBR structures. (b) Zoomed-in view of the reflectance at peak values to illustrate more clearly the disparity in optical performance between the LC and HC structures.

In Fig. 11 we compare all the proposed designs from the electrical performance point of view at 10K, the lowest temperature we could simulate.

Fig. 11.

Voltage (lines) and differential resistance (dash-lines) versus applied current for the base p-DBR structure (Sample 1), uni-parabolically graded p-DBR, and low and high refractive index contrast p-DBRs with four and five interface layers. V, R, HC, and LC mentioned in the legend are referred to as voltage, differential resistance, high-contrast, and low-contrast respectively.

We opted for 17 periods for LC-DBRs to ensure a fair comparison, as they exhibit the same optical performance as the HC-DBRs in this scenario.

The characteristics in Fig. 11 indicate that the proposed structure with low refractive-index contrast of DBR layers featuring five step-like interfaces is comparable in efficiency to the uni-parabolically graded p-DBR, with less complexity and time needed for growth even with more pairs of layers (two more pairs). It can be inferred that for the uni-parabolically graded p-DBR and the low-contrast five step-like interfaces p-DBRs, the voltage penalty improved by 50% and 39%, respectively, at a 25 mA driving current. On the other hand, the differential resistance at a current density of 5 kA/cm² improved by 74% and 60% for the uni-parabolically graded p-DBR and the low-contrast five step-like interfaces p-DBRs, respectively.

SECTION V. Conclusion

The operation of p-DBRs used in VCSELs was estimated in different cryogenic temperature environments. The simulation shows a significant increase in the temperature of the operating device at cryogenic temperatures, resulting from both the low thermal energy of the carrier and the low thermal conductivity of the material at those extremely low temperatures. Using the data obtained from the thermal analysis, detailed characteristics of DBR designs with different types of interfaces were simulated. Results show that by properly designing the p-DBRs, which are the main source of series resistance in the VCSEL having conducting mirrors, the series resistance can be improved by 74% and 60% at a current density of 5 kA/cm² at the 10 K temperature. The optimal operation is ensured by two geometries of layer interfaces: uni-parabolically grading and five step-like interfaces for a low refractive index contrast p-DBR. Moreover, the voltage penalty can also be improved by 50% and 39% for these structures, respectively.