Periphery Gate Optimization for Reducing Single-Sense Amp (SSA) Failure in DRAM: YE: Yield Enhancement/Learning

The paper presents a potent approach to enhancing front-end yield. It underscores a multifaceted issue that originates from various modules, illustrating the intricacy and significance of evaluating process interactions across layers. The paper showcases how a well-structured and data-driven problem-solving technique can effectively tackle a complex problem. This work lays the groundwork for enhancing other package-level testing issues and opens up further opportunities for process margin enhancement. It details the issue of misalignment between periphery gate contacts and the periphery gate for sense amplifiers. The problem intensifies when the underlying active area is larger, leading to the electrical shortening of the gate to source/drain contact. Alongside various efforts to improve the overlay, the issue was substantially mitigated by addressing it through gate length and contact target optimization, followed by a reticle edit for the active area at the failure location.