A Reduced-Order Digital Twin FPGA-Based Implementation With Self-Awareness Capabilities for Power Electronics Applications

Developing accurate mathematical or data-driven models for effective controller design under dynamic variable conditions becomes increasingly challenging. For this reason, the concept of a digital twin (DT) as a virtual representation of a physical asset has been introduced as a tool for process modelling, design, and control implementation while providing additional knowledge of the system that can be used to enable awareness capabilities on the asset. However, digital twin models used to be complex, requiring expensive computational times depending on the application to provide the most accurate system representation, limiting its application in edge, embedded, and register transfer level computing domains. Therefore, using reduced-order digital twin models is an alternative to get DT closer to the physical asset. Considering these challenges, we propose a reduced-order FPGA-based digital twin implementation that directly sources data from the real system, operates in parallel with the virtual system, and enables awareness mechanisms to improve the system’s operation. This setup removes large data transfers, cloud interfaces and expensive computational times deriving into a faster and more efficient DT. To illustrate the capabilities of this embedded digital twin, we present a case study focused on monitoring a power converter. The study involves establishing and enforcing a safe operating area (SOA) for the power converter, implementing error awareness mechanisms, and enabling machine learning models to predict converter load conditions and fault events detection. Thus, we aim to showcase the effectiveness of our proposed FPGA-based digital twin approach in addressing real-time control challenges towards smart control engineering.