ESD Architecture and Floor Planning

Summary

This chapter aims to teach how to construct a semiconductor chip to achieve an electrostatic discharge (ESD) robust implementation. The ordering of materials in this chapter is constructed in the same fashion that a semiconductor chip is assembled. The chapter begins by discussing the architecture and layout floor planning for different chip architectures. The discussion addresses both peripheral and “array” I/O configurations. In peripheral I/O design, the wire bonds and packaging requirements limit the number of I/O cells placed on the periphery of the semiconductor chip. Product application types that are typically peripheral I/O with core‐limited applications are typically low pin‐count chips that require large arrays, or large devices. ESD power clamps can be integrated into the individual signal pad “cell,” or more common is the placement as a “lumped” element in the semiconductor chip. The chapter discusses the integration of lumped ESD power clamps.