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3D Design‐for‐Test Architecture | part of Handbook of 3D Integration, Volume 4: Design, Test, and Thermal Management | Wiley Semiconductors books | IEEE Xplore

3D Design‐for‐Test Architecture

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Chapter Abstract:

Summary IMEC and Cadence have jointly developed a 3D design‐for‐test (DfT) architecture that serves both 2.5D and 3D stacked integrated circuits (SICs). The architecture ...Show More

Chapter Abstract:

Summary

IMEC and Cadence have jointly developed a 3D design‐for‐test (DfT) architecture that serves both 2.5D and 3D stacked integrated circuits (SICs). The architecture originally targeted stacks of monolithic, non‐hierarchical, logic‐only dies. A 3D‐DfT demonstrator circuit was designed, manufactured, and tested as part of an IMEC 3D chip stack nicknamed “Vesuvius‐3D.” Over time, our architecture has been extended to include (i) multi‐tower stacks, hierarchical system on chips (SoCs) containing (ii) test data compression and (iii) embedded cores, (iv) allow for at‐speed interconnect testing, and (v) cover memory‐on‐logic stacks.

Page(s): 253 - 280
Copyright Year: 2019
Edition: 1
ISBN Information: