Test and Debug Strategy for TSMC CoWoS ® Stacking Process‐Based Heterogeneous 3D‐IC: A Silicon Study

Summary

TSMC has developed the Chip‐on‐Wafer‐on‐Substrate (CoWoS^®) process as a design paradigm to assemble silicon interposer‐based 3D‐ICs. To reach quality requirements for volume production, several test challenges related to 3D‐ICs need to be addressed. This chapter describes the test and diagnosis solutions for the challenges that were faced in designing a CoWoS^® process‐based heterogeneous memory‐on‐logic and logic‐on‐logic 3D‐IC. The objective of this design was to find the stacking process weaknesses in creating a stacked die system consisting of multiple dies in different technologies (logic and memory). It is also used to demonstrate the strength of the stacking capability when dies to be stacked are sourced from different vendors. The design contains three dies: system‐on‐chip die (logic), DRAM die (logic), and JEDEC WideIO DRAM die (memory). The chapter demonstrates how the design‐for‐diagnosis features implemented on the logic die were used to isolate interconnect testing failures.