FPGA and Embedded Software Implementation for Dragonfly Spacecraft Interface Card

This paper describes the architecture of the Spacecraft Interface (SCIF) Card FPGA and corresponding soft processor implemented for NASA’s New Frontiers Dragonfly mission to Titan. The SCIF FPGA has a flexible architecture designed to facilitate dataflow between various payloads and peripherals, accommodating a variety of spacecraft configurations. Supported protocols include PCI, SpaceWire, UART, SPI, and I2C interfaces.The internal AMBA bus is segmented into two portions and connected via an AHB/AHB bridge: an AHB bus primarily mastered by Flight Software running on a Single Board Computer (SBC) accessed over a PCI/AHB bridge, and another AHB bus mastered by a LEON soft processor. Both buses are highly modular and allow for individual interfaces to be instantiated or deactivated at FPGA compile time. In the Dragonfly mission application, SCIF FPGA facilitates commanding and telemetry collection across the various interfaces. It also supports the LEON soft processor and SBC Flight Software application code storage, as well as boot processes, vets, and distributing timekeeping information across the spacecraft. It also supports direct Hardware Commanding via specialized commands which have been received from the Spacecraft Radio. Lastly, it controls access to the mission Solid State Recorder (SSR) which houses collected science data.The soft LEON processor facilitates data movement by serving as a master on the secondary AHB bus whereby it stores data in the onboard SRAM for later collection by the Single Board Computer. The LEON also configures the SCIF FPGA registers at boot time for application specific functionality. This has the benefit of allowing for design flexibility without a required FPGA re-build. The second revision of the SCIF FPGA and LEON Flight Software is currently undergoing development, and will target the Engineering Module of the SCIF Board.